Commit graph

879,378 commits

Author SHA1 Message Date
qctecmdr
4fb04ec2bf Merge "iommu/arm-smmu: Add support for implementation specific debugging" 2020-03-20 09:40:40 -07:00
qctecmdr
3b90a3b235 Merge "msm: kgsl: remove redundant check for usermem type" 2020-03-20 05:55:01 -07:00
qctecmdr
1150df1e70 Merge "msm: ADSPRPC: Awake PM with a timeout" 2020-03-20 05:55:00 -07:00
qctecmdr
c18b56730d Merge "soc: qcom: socinfo: Add soc information for Shima" 2020-03-20 01:15:50 -07:00
qctecmdr
c81d459676 Merge "ion: Fix to record NR_KERNEL_MISC_RECLAIMABLE in page units" 2020-03-20 01:15:49 -07:00
qctecmdr
12d4640529 Merge "sched: Add support to spread tasks" 2020-03-20 01:15:49 -07:00
qctecmdr
fa0c7b3eb6 Merge "drivers: lpm-levels: check for per-cpu dev PM QoS" 2020-03-20 01:15:48 -07:00
Raghavendra Rao Ananta
6c1e5e4534 arm64: defconfig: Enable debugging support for spinlocks
Enable CONFIG_DEBUG_SPINLOCK to debug issues with respect to
deadlocks on Lahaina platforms.

Change-Id: I9599e3478118c1decdfe7a0b2c76064e710ef9f3
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
2020-03-19 06:47:02 -07:00
Chandra Sai Chidipudi
9f5985196b soc: qcom: socinfo: Add soc information for Shima
Add SOC ID to support socinfo for Shima SOC.

Change-Id: I2f3c8476d02ab55e55d14c64e359a1a2a5deeafd
Signed-off-by: Chandra Sai Chidipudi <cchidipu@codeaurora.org>
2020-03-19 06:24:59 -07:00
qctecmdr
ad8b0e3fc3 Merge "msm: kgsl: Finish up probe cleanups" 2020-03-18 19:19:21 -07:00
Lingutla Chandrasekhar
50a9295169 sched: Add support to spread tasks
If sysctl_sched_prefer_spread is enabled, then tasks would be freely
migrated to idle cpus within same cluster to reduce runnables.

By default, the feature is disabled.
User can trigger feature with:
   echo 1 > /proc/sys/kernel/sched_prefer_spread
	Aggressively spread tasks with in little cluster.
   echo 2 > /proc/sys/kernel/sched_prefer_spread
	Aggressively spread tasks with in little cluster as well as
	big cluster, but not between big and little.

Change-Id: I0a4d87bd17de3525548765472e6f388a9970f13c
Signed-off-by: Lingutla Chandrasekhar <clingutla@codeaurora.org>
[satyap@codeaurora.org: fix trivial merge conflicts]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2020-03-18 12:41:02 -07:00
Isaac J. Manjarres
f715a4c183 iommu/arm-smmu: Add support for implementation specific debugging
Certain SMMU implementation, such as the QSMMUV500 model, have
hardware that can be used to collect information that is useful
for debugging adversarial scenarios, such as TLB sync timeouts.

Add support for collecting information for debugging TLB sync
timeouts, as well as triggering the SMMU HW to perform a
translation for verification purpose, and wire up the QSMMUV500
implementations of these hooks. In doing so, there are no
users of the iova_to_phys_hard() and tlb_sync_timeout() hooks
in the arm_smmu_arch_ops structure, so remove these fields.

Change-Id: I61df57e82f3058a7e8a09f4df1fe147a71ae2fc3
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-03-18 10:28:53 -07:00
Isaac J. Manjarres
1189ad27e6 iommu/arm-smmu: Add implementation specific CB initialization hook
Some SMMU implementations, such as the QSMMUV500 model, may
need to program a specific context bank, in addition to the
initial context bank programming. Thus, add support for
implementation specific context bank initialization, and
migrate the QSMMUV500 context bank initialization to use
the new hook.

Consequently, as there are no current users of the
arm_smmu_arch_init_context_bank() hook, remove it.

Change-Id: Ia89420cc8b669a142b37bf4250c09b6aa3646172
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-03-18 10:28:53 -07:00
Isaac J. Manjarres
5b66300440 iommu/arm-smmu: Rework QSMMUV500 initialization
Rework the QSMMUV500 initialization sequence, such that the
QSMMUV500 implementation initialization uses the existing
SMMU implementation architecture.

This means ensuring that all of the implementation specific
data structures are allocated as part of the initialization,
as well as ensuring that all of the TBUs have probed. Also,
move the logic for hardware version detection to the QSMMUV500
configuration probe function.

Consequently, there are now no users of the arm_smmu_arch_init()
and arm_smmu_arch_device_reset() hooks, so remove them.

Change-Id: I8ca82ef8ea821b9e2171f7dca707f4da6ce2c0d7
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-03-18 10:28:52 -07:00
Isaac J. Manjarres
3729473791 iommu/arm-smmu: Prepare to migrate QSMMUV500 implementation details
All of the implementation details related to the QSMMUV500 model
of the SMMU-V2 architecture currently reside in arm-smmu.c.
This clashes with the current ARM SMMU SW architecture, as
arm-smmu.c is meant to house architecture specific details,
and arm-smmu-[$VENDOR].c is meant to house vendor specific
implementation details about those architectures.

To prepare to move to comply with this architecture, migrate
the QSMMUV500 related logic to arm-smmu-qcom.c, as well as
export any shared data structures. This patch should not
introduce any functional changes.

Change-Id: I711e41e38cd35b6727faf5a399eefcf5db453612
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-03-18 10:28:39 -07:00
Anirudh Raghavendra
ece1046cb9 msm: ADSPRPC: Awake PM with a timeout
Awake PM with a timeout in kernel soon after response from DSP to
keep the system awake and allow the ioctl call reach user space from
kernel space.

Change-Id: If518e17ec300565af2d16feca0524e741790ba7f
Acked-by: Himateja Reddy <hmreddy@qualcomm.com>
Signed-off-by: Anirudh Raghavendra <araghave@codeaurora.org>
Signed-off-by: Edgar Flores <edgarf@codeaurora.org>
2020-03-17 23:26:37 -07:00
qctecmdr
816c0efa14 Merge "defconfig: lahaina: Enable GPU driver" 2020-03-17 19:37:11 -07:00
qctecmdr
cf314fc5c9 Merge "msm: cvp: Disable CVP_DBG traces by default" 2020-03-17 19:37:10 -07:00
qctecmdr
22de23501b Merge "wil6210: Add support for 11ad platform driver" 2020-03-17 19:37:10 -07:00
qctecmdr
5c91c43dcd Merge "net: qrtr: mhi: Set mhi driver data before registering with qrtr" 2020-03-17 19:37:10 -07:00
qctecmdr
9829d2c4b3 Merge "defconfig: Disable fastrpc driver from kernel image" 2020-03-17 19:37:09 -07:00
Maria Yu
2b0e26d3a8 sched/fair: Allow load bigger task load balance when nr_running is 2
When there is only 2 tasks in 1 cpu and the other
task is currently running, allow load bigger task
to be balanced if the other task is currently
running.

Change-Id: I489e9624ba010f9293272a67585e8209a786b787
Signed-off-by: Maria Yu <aiquny@codeaurora.org>
Signed-off-by: Cong Zhang <congzhan@codeaurora.org>
2020-03-17 17:09:15 -07:00
Liam Mark
43d6288fbb ion: Fix to record NR_KERNEL_MISC_RECLAIMABLE in page units
Currently NR_KERNEL_MISC_RECLAIMABLE is being updated with units of bytes.
Fix to correctly update NR_KERNEL_MISC_RECLAIMABLE using page units.

Change-Id: Ie6c620a2a2218be1b30e9f1539c9d0d92870a726
Signed-off-by: Liam Mark <lmark@codeaurora.org>
2020-03-17 17:05:36 -07:00
Lingutla Chandrasekhar
a21fe9c3d8 sched: Improve the scheduler
This change is for general scheduler improvements.

Change-Id: I780f52ebc3cb69ee2c497d2d2f8e8fddd789421d
Signed-off-by: Lingutla Chandrasekhar <clingutla@codeaurora.org>
2020-03-17 16:10:51 -07:00
Pavankumar Kondeti
eb329acdbb sched/fair: reduce no-hz idle balance for energy aware systems
We are kicking no-hz idle balance when the CPU has two tasks.
It should be done only when the CPU is overutilized on
energy aware systems. This approach seems to be causing more
number of wakeups on HZ=250 systems compared to HZ=100.

Revisit the no-hz idle scheme and only send the IPI if and
when it is necessary.

Change-Id: I82e58a2aa3b6508c86d05c93c9fb7fe6dfbde500
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
[satyap@codeaurora.org: fix trivial merge conflicts]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2020-03-17 16:08:17 -07:00
qctecmdr
262793ca89 Merge "msm: kgsl: Use booleans for power control features" 2020-03-17 13:33:00 -07:00
Edgar Flores
ca8a9670fa defconfig: Disable fastrpc driver from kernel image
Disable fastrpc driver from Lahaina kernel image.

Change-Id: Iee1594be32934dc93b932107f8a16062f1a1e068
Signed-off-by: Edgar Flores <edgarf@codeaurora.org>
2020-03-17 12:26:39 -07:00
Lina Iyer
7335b12cc0 drivers: lpm-levels: check for per-cpu dev PM QoS
Drivers may request a QoS latency on a CPU using the dev_pm_qos
framework. Check for DEV_PM_QOS_RESUME_LATENCY as well while selecting
the idle state for a CPU and for all the CPUs in a cluster to select the
best idle state for the cluster.

Change-Id: Ic4e18f05ef8a09a8f668b89b9973f8e8499d7e02
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
2020-03-17 11:49:06 -06:00
qctecmdr
2fdb6c48bd Merge "msm: cvp: Reduce CVP dmabuf mapping overhead" 2020-03-17 09:20:19 -07:00
qctecmdr
93e87a288c Merge "arm64: kpti: force off kpti" 2020-03-17 09:20:18 -07:00
qctecmdr
2248785891 Merge "scsi: ufs-qcom: Add one vendor specific sysfs group" 2020-03-17 09:20:18 -07:00
qctecmdr
c160f5998e Merge "arm64: defconfig: Enable ION support on genericarmv8-64_defconfig" 2020-03-17 09:20:18 -07:00
Alexei Avshalom Lazar
5a5260fe01 wil6210: Add support for 11ad platform driver
Platform driver used to handle msm specific platform
requirement for 11ad chipset connected to msm platform.

Change-Id: I13c5b5a76bc17393e486c400bdfb90e4ef89e270
CRs-Fixed: 2143032
Signed-off-by: Alexei Avshalom Lazar <ailizaro@codeaurora.org>
[liord@codeaurora.org: SPDX license, checkpatch errors]
Signed-off-by: Lior David <liord@codeaurora.org>
2020-03-17 08:32:32 -07:00
qctecmdr
c101c53524 Merge "clk: qcom: lahaina: Add sync_state callbacks" 2020-03-17 06:50:39 -07:00
qctecmdr
9e370393b3 Merge "arm64: defconfig: Enable QTI_IOMMU_SUPPORT only on target configurations" 2020-03-17 04:27:28 -07:00
qctecmdr
f2c2ad2be1 Merge "interconnect: qcom: Fix uninitialized tcs_cmd::wait" 2020-03-17 04:27:28 -07:00
qctecmdr
8cd651ce9c Merge "usb: gadget: f_diag: Expose DLOAD pid/serial entries to configfs" 2020-03-17 04:27:27 -07:00
qctecmdr
a7d9ad8821 Merge "msm: kgsl: Enable apb clock before isdb register writes" 2020-03-17 04:27:27 -07:00
Can Guo
a0289684e3 scsi: ufs-qcom: Add one vendor specific sysfs group
Add one vendor specific sysfs group to support additional sysfs nodes,
such as err_state and power_mode.

Change-Id: Ia69909fc3838a054221191259a015067dd962008
Signed-off-by: Can Guo <cang@codeaurora.org>
2020-03-17 01:56:13 -07:00
Vinayak Menon
1edf9722d4 arm64: kpti: force off kpti
Since most of the CPUs aren't prone to meltdown,
force off the kpti feature. Enable on required
targets.

Change-Id: If78c70bcaeac2b157a901e5036190aaf9e5aabf6
Signed-off-by: Vinayak Menon <vinmenon@codeaurora.org>
2020-03-16 23:46:49 -07:00
qctecmdr
fafcdeebed Merge "trace: Add warning threshold for irqsoff time" 2020-03-16 22:55:50 -07:00
qctecmdr
d1f345796a Merge "scsi: ufs-qcom: Configure LPM timer settings" 2020-03-16 22:55:50 -07:00
qctecmdr
f0e348558a Merge "msm: kgsl: Fix to record NR_KERNEL_MISC_RECLAIMABLE in page units" 2020-03-16 22:55:49 -07:00
George Shen
b1d298dc7a msm: cvp: Reduce CVP dmabuf mapping overhead
To reduce computation overhead in searching and matching un-used
or used CVP iommu mappings.

Change-Id: I57f2849c1fcd81d534bb55f24b51b66d3b321cb4
Signed-off-by: George Shen <sqiao@codeaurora.org>
2020-03-16 20:21:57 -07:00
qctecmdr
d3fc7ea1c3 Merge "leds: qti-flash: Add support for on_time and off_time parameters" 2020-03-16 20:03:19 -07:00
qctecmdr
b2d9f86807 Merge "haven: doorbell: Add neuron and qrtr labels" 2020-03-16 20:03:18 -07:00
qctecmdr
2c406b9ecf Merge "sched/fair: Change PELT half-life to 8ms" 2020-03-16 20:03:18 -07:00
Jordan Crouse
9cfc90b482 defconfig: lahaina: Enable GPU driver
Enable the GPU driver and the dependent QFPROM driver.

Change-Id: Ic0dedbadf13a34d778bec51151d1c9f00e29a258
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
2020-03-16 13:08:47 -06:00
Mohammed Mirza Mandayappurath Manzoor
3c339456eb msm: kgsl: Enable apb clock before isdb register writes
KGSL must enable the apb clock before accessing QDSS register space.

Change-Id: I4fb20741c54ef665bf2652c13c4c87fd9b0b3329
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <mmandaya@codeaurora.org>
2020-03-16 12:05:56 -07:00
George Shen
7bb1a82ce9 msm: cvp: Disable CVP_DBG traces by default
It caused tracing spam in kernel log.

Change-Id: Iaddb5e95138638b6dbfe63e51eb14db80a202c9d
Signed-off-by: George Shen <sqiao@codeaurora.org>
2020-03-16 10:35:02 -07:00