Commit graph

348 commits

Author SHA1 Message Date
qctecmdr
541da47199 Merge "drm/msm: perform mode fixup against current state" 2019-07-27 09:33:20 -07:00
qctecmdr
89b080516e Merge "disp: msm: update min prefill lines for sde rsc" 2019-07-27 07:54:34 -07:00
qctecmdr
9908bdb083 Merge "disp: msm: dp: Enable pre-emphasis level 3" 2019-07-27 07:06:22 -07:00
qctecmdr
81c67c168d Merge "disp: msm: dp: add support for test pattern #4" 2019-07-27 06:17:11 -07:00
qctecmdr
9ab3075070 Merge "disp: msm: dp: adding prefix for logs" 2019-07-27 05:25:11 -07:00
qctecmdr
bb300b0511 Merge "disp: msm: sde: Add LTM sw fuse check support" 2019-07-27 04:36:40 -07:00
qctecmdr
2a75326609 Merge "disp: msm: sde: Add event log for uidle veto enable" 2019-07-27 03:47:20 -07:00
qctecmdr
6ad46f19c3 Merge "disp: msm: Use the new notifier function instead of msm_drm_notifier" 2019-07-26 17:45:17 -07:00
qctecmdr
bc91692047 Merge "disp: msm: sde: avoid input handler of registration in video mode" 2019-07-26 09:14:09 -07:00
qctecmdr
91edc96425 Merge "disp: pll: limit clock rate of shadow VCO clock" 2019-07-26 06:42:29 -07:00
qctecmdr
abb4577e29 Merge "disp: msm: sde: consider num DS for mixer width" 2019-07-26 05:18:05 -07:00
qctecmdr
1cc7a54215 Merge "disp: msm: sde: fix crtc client type checks for WB" 2019-07-26 04:06:40 -07:00
qctecmdr
51e3c33c7d Merge "disp: msm: sde: add check before buffer copy" 2019-07-26 02:56:37 -07:00
qctecmdr
c9c060d40c Merge "disp: msm: dsi: add check before buffer copy" 2019-07-26 01:33:26 -07:00
qctecmdr
1cf6ef4a2c Merge "disp: msm: hdcp: update encryption level on framework request" 2019-07-26 00:21:37 -07:00
Dhaval Patel
bb3fee993c disp: msm: update min prefill lines for sde rsc
Update minimum prefill lines for command mode
displays based on system recommendation for
different fps. Video mode display can support
prefill lines based on panel porches.

Change-Id: I52dc67035fa80668281926ce4d7dd1b292fbc3b7
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2019-07-25 17:28:36 -07:00
Ajay Singh Parmar
2d4ac9b559 disp: msm: dp: Enable pre-emphasis level 3
Enable the pre-emphasis level 3 as per hardware recommendations.

CRs-Fixed: 2490128
Change-Id: I649b0cb79c1c5f5d92d2265d9ff2058c2ca81c16
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
2019-07-25 14:43:40 -07:00
Satya Rama Aditya Pinapala
2078f3dd2e disp: msm: sde: add check before buffer copy
This change adds a check for the length of the buffer
before copying it to avoid a buffer overflow.

Change-Id: I9af9d422e0b3cf02c8d6662af3310337a9861a7a
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2019-07-25 10:57:26 -07:00
Yujun Zhang
80d06ebb7c disp: pll: limit clock rate of shadow VCO clock
Limit clock rate of shadow VCO clock as normal VCO clock.
For larger bit clock rate gap between switched ones, the clock switching
would fail due to mismatched VCO clock rate between normal VCO clock and
shadow one.

Change-Id: I9d68725de360ac28c243a3ce1800bfb139f39757
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
2019-07-25 02:38:39 -07:00
Veera Sundaram Sankaran
f61e5545d7 disp: msm: sde: fix crtc client type checks for WB
CRTC client type is wrongly identified as RT_CLIENT
for WB as the API considers only RT and RT_RSC. Resolve
it by adding a new API to check for RT CTRC.

Change-Id: I1f216f60a18215426e594d0f8b09852af376799d
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2019-07-24 14:52:42 -07:00
Lei Chen
92fe6638ed disp: msm: sde: avoid input handler of registration in video mode
Input handler is used for early wakeup DSI and MDP clocks from
idle power collapse. DSI clock won't be disabled in video mode
during idle power collapse, so the input hanlder isn't needed
for video mode.
This change avoids the input handler to be registered in
video mode.

Change-Id: Id23bad192b6671126978d707db464e7aaee1c77f
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
2019-07-24 09:33:35 +08:00
Ajay Singh Parmar
9af9987d3d disp: msm: dp: add support for test pattern #4
DP specification mandate test pattern #4 for CTS 1.4a. Add
support for the same in link training #2 as per specification.

CRs-Fixed: 2490128
Change-Id: I2f72fec340b56270e7fd1c2940adafe1068bab43
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
2019-07-23 15:43:26 -07:00
Nilaan Gunabalachandran
1e06ddddc3 disp: msm: sde: Add event log for uidle veto enable
Print uidle status fal10 enable bit as part of checking status.

Change-Id: Ibe00216ac22bb31fbe0925db3abc1d5dc4371ad3
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2019-07-23 16:22:16 -04:00
Satya Rama Aditya Pinapala
804f6e0de2 disp: msm: dsi: add check before buffer copy
This change adds a check for the length of the buffer
before copying it to avoid a buffer overflow.

Change-Id: I146895660be4060d9896706636257a57c6aef94f
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2019-07-23 09:22:26 -07:00
Nilaan Gunabalachandran
233ded8506 disp: msm: sde: consider num DS for mixer width
Helper function is returning the width of single mixer. During
atomic crtc check, the number of destination scaler is not
considered before width check and can fail possible higher
resolutions. The mixerwidth should be taken as a multiple of
num_ds_enabled.

Change-Id: Id9e5e0ccf0cebb54d2a242e039d8dc3676b3729f
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2019-07-23 12:20:41 -04:00
Satya Rama Aditya Pinapala
aacd9e9585 disp: msm: dp: adding prefix for logs
Adding prefixes for error, debug and info
messages in dp files. To enable debug logs
run "echo 0x100 > /sys/module/drm/parameters/debug"

CRs-Fixed: 2493739
Change-Id: Ibf509e837f527be6bff6b7a1c34b0cde2921b388
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2019-07-23 09:14:04 -07:00
qctecmdr
a6bfb7fc1e Merge "disp: msm: dsi: adding prefix for logs" 2019-07-23 01:20:03 -07:00
qctecmdr
d393bfcf01 Merge "disp: msm: dp: split host init and deinit" 2019-07-22 23:21:57 -07:00
qctecmdr
04dcddd7c0 Merge "disp: msm: dsi: update default physical panel width and height" 2019-07-22 21:20:22 -07:00
Tatenda Chipeperekwa
a382d900a3 disp: msm: hdcp: update encryption level on framework request
Update the minimum encryption level only when there is a request
to do so coming from the DRM framework. This will ensure that any
previously set value will not be overwritten while processing
other commands. Failure to preserve the minimum encryption level
can result in secure content playback failure if the sink device
is not updated with the correct value.

Change-Id: Ie9a555a57617096fbdb9e46dd29a973b9223e237
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
2019-07-22 17:59:50 -07:00
Satya Rama Aditya Pinapala
6c483e3b23 disp: msm: dsi: adding prefix for logs
Adding debug, info and error prefix for log messages
in dsi files. To enable debug logs
run "echo 0x1 > /sys/module/drm/parameters/debug"

Change-Id: I438ac16954bd1d39450f8adeb7fb17f9ea6f8140
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2019-07-22 17:43:35 -07:00
qctecmdr
708c74de1e Merge "drm/msm: allow sde_atrace to show up on different process" 2019-07-22 17:35:07 -07:00
qctecmdr
c8aa6f7e44 Merge "drm/msm: enable counter trace" 2019-07-22 15:50:30 -07:00
qctecmdr
f95b75fdc6 Merge "drm/msm/sde: fix unpaired sde trace" 2019-07-22 13:55:17 -07:00
qctecmdr
3588284310 Merge "disp: msm: sde: fix cwb, dp and wb tear down sequence" 2019-07-22 11:52:53 -07:00
Ajay Singh Parmar
59008eabf8 disp: msm: dp: split host init and deinit
Break the host initialization and de-initialization to
create late initialization and early de-initialization.
Call host init/deinit on physical connect/disconnect only
As attention messages from sink doesn't change the physical
cable configurations, call only late init/early deinit in
this case to avoid unnecessary hardware resources
re-initialization.

CRs-Fixed: 2490128
Change-Id: Ib930d250724ab3ea811a7388c7ad0aeae1164e21
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
2019-07-19 13:45:56 -07:00
qctecmdr
82a67564fb Merge "disp: msm: dsi: signal pending clock change in case of DMS" 2019-07-19 05:17:06 -07:00
qctecmdr
829a9ba490 Merge "disp: msm: sde: correct the highest bank bit configuration." 2019-07-19 05:17:06 -07:00
qctecmdr
f23d62f8b1 Merge "disp: msm: dsi: update DSI PHY sequence for Kona" 2019-07-19 05:17:06 -07:00
qctecmdr
e9482e9e43 Merge "disp: msm: dsi: update dsi pclk in panel mode settings" 2019-07-19 05:17:06 -07:00
qctecmdr
9e4f9dab61 Merge "disp: msm: dsi: remove using static memory for roi commands" 2019-07-19 05:17:06 -07:00
qctecmdr
6db1b4cad1 Merge "disp: msm: dsi: Set the panel test gpio to input" 2019-07-19 05:17:06 -07:00
qctecmdr
73175fb95a Merge "disp: msm: sde: Correct initialization value for frame count" 2019-07-19 05:17:05 -07:00
Yuan Zhao
f2fdcee320 disp: msm: dsi: Set the panel test gpio to input
This GPIO is a input signal, so need to set it
to input mode, or it will lead leakage in RBC.
This change is only to fix the power issue.

Change-Id: I87716f646c75dac2f1350a2ea55188829a4ccc9e
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
2019-07-19 00:52:34 -07:00
Yuan Zhao
a7b5db0465 disp: msm: dsi: Add a new DT property panel test pin
This pin is a output pin from panel. Panel can
output signal of internal VSYNC and ERR_FLAG.

Change-Id: Ib8e661ca1fdb33bb7060935edb9bc1f1a858c4b3
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
2019-07-18 23:01:02 -07:00
Vara Reddy
30d6730b20 disp: msm: dsi: update dsi pclk in panel mode settings
Change calculates and updates correct pclk that is being
used to drm modes in kilo hertz.

Change-Id: I7aab10c08689697120d4d7c152f30993defd36d3
Signed-off-by: Vara Reddy <varar@codeaurora.org>
2019-07-18 15:42:01 -07:00
Vara Reddy
8915522efc disp: msm: dsi: remove using static memory for roi commands
Partial update commands are using static memory. For dual dsi,
both dsi's can manipulate on same memory, if partial update is enabled
on both of them. Change removes the static configuration.

Change-Id: I0ca16324a27427d13deaa9d18e3ab4f47fe1cc21
Signed-off-by: Vara Reddy <varar@codeaurora.org>
2019-07-18 14:23:28 -07:00
Dhaval Patel
bcd97aa368 disp: msm: sde: fix cwb, dp and wb tear down sequence
CWB, DP and WB displays tear down sequence must reset
3d_merge, ctl, pingpong_binding, etc. MDP HW
blocks. This change fixes the tear down
sequence register programming. It also moves flush
sw reset before encoder_disable call. That allows
CWB tear down to update the flush configuration
on primary ctl path.

Change-Id: I21c521b39456af4144cf836c65d46a25c985f51d
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2019-07-18 14:13:33 -07:00
Satya Rama Aditya Pinapala
db61fc7518 disp: msm: dsi: update DSI PHY sequence for Kona
This change updates the DSI PHY sequence for Kona target as
per latest HW team recommendation.

Change-Id: I20f6a81bb1112e9e976acae595b985dad7ad4b7a
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2019-07-18 13:59:05 -07:00
Satya Rama Aditya Pinapala
7ea04a4d47 disp: pll: update DSI PHY PLL programming for Kona
This change updates the DSI PHY PLL programming for kona target
as per the hardware recommendation.

Change-Id: I706169fb635e72bd0ccd3057107ea749408733d0
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2019-07-18 12:41:38 -07:00