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883,895 commits

Author SHA1 Message Date
Satya Rama Aditya Pinapala
5b0306566e aarch64: ABI: add symbols to qcom whitelist
Change adds unmap_kernel_range, get_vm_area, and
ioremap_page_range to qcom whitelist and update the
ABI snapshot.

Change-Id: I34e3a976f68281b7937719f62379002cb7bf6d93
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2020-05-27 14:15:52 -07:00
qctecmdr
17439c2c67 Merge "soc: qcom: Add VTCM handling to cdsprm driver" 2020-05-27 08:45:22 -07:00
qctecmdr
edebc0ccbb Merge "Revert "arm: dma: Allow CMA pages to not have a kernel mapping"" 2020-05-27 08:45:22 -07:00
Bavyasritha Alahari
694724873c soc: qcom: Add VTCM handling to cdsprm driver
VTCM handling in cdsp request manager, reads the device
tree as part of platform driver registration notifier and
sends the data to guestos driver via rpmsg channel and
exposes methods to override partition mapping via
debugfs node.

Change-Id: Ie28e750f0a27f35ec114278aa0b87952ecda70f6
Acked-by: Sreekanth Gande <sgande@qti.qualcomm.com>
Signed-off-by: Bavyasritha Alahari <alahari@codeaurora.org>
2020-05-27 16:25:46 +05:30
Qingqing Zhou
cce1d3c648 Revert "arm: dma: Allow CMA pages to not have a kernel mapping"
This reverts commit 0b06cd5ca5.

The meaning of DMA_ATTR_NO_KERNEL_MAPPING changes, it will not remove
kernel mapping, just return the page pointer directly, so make 32 bit
align with 64 bit.

Change-Id: I905f2faa11681dff745191928345fef00c9ec796
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-27 18:17:19 +08:00
qctecmdr
8f9e82655d Merge "net: qrtr: Ignore ENODEV failures in ns" 2020-05-27 00:13:42 -07:00
qctecmdr
c05ee13d5e Merge "NFC: Enable NFC driver in the GKI build" 2020-05-27 00:13:42 -07:00
qctecmdr
c606037c2d Merge "mm: Remove shrink_page" 2020-05-27 00:13:41 -07:00
Karthik Poosa
eca0dbcda6 NFC: Enable NFC driver in the GKI build
Add NFC I2C driver as loadable module.

Change-Id: Ib6188940c850f63a458b6bf0eba6b35a2b898362
Signed-off-by: Karthik Poosa <kpoosa2@codeaurora.org>
2020-05-26 20:41:41 -07:00
qctecmdr
58f1b8ccb0 Merge "ARM: dts: msm: Create softlink for vendor specific dt" 2020-05-26 19:58:21 -07:00
qctecmdr
32e550cb6b Merge "soc: qcom: socinfo: Add LAHAINAP's soc-id" 2020-05-26 19:58:21 -07:00
qctecmdr
29fc359d04 Merge "aarch64: ABI: Remove slim_* APIs from whitelist" 2020-05-26 19:58:21 -07:00
qctecmdr
44978760c1 Merge "thermal: adc-tm: Ensure valid match data is obtained" 2020-05-26 19:58:20 -07:00
qctecmdr
e7b04640ad Merge "net: qrtr: Fix error pointer vs NULL bugs" 2020-05-26 19:58:20 -07:00
Chris Lew
e5bbd357d9 net: qrtr: Ignore ENODEV failures in ns
Ignore the ENODEV failures returned by kernel_sendmsg(). These errors
mean either the local port has closed or the remote has gone down.
Neither of these scenarios are fatal and will eventually be handled
through packets that are later queued on the control port.

Also improve the logging messages to print the error code returned by
kernel_sendmsg().

Change-Id: Ibcebd1f44a3fbc87febaa84b11e05675663da5a0
Signed-off-by: Chris Lew <clew@codeaurora.org>
2020-05-26 10:16:56 -07:00
Chris Lew
617ffc4bf4 net: qrtr: Add pr_fmt to ns
Add pr_fmt to the ns file for easier error log matching.

Change-Id: I711735ee60c1fd9fde25850b8e625bb44c04f4c4
Signed-off-by: Chris Lew <clew@codeaurora.org>
2020-05-26 10:16:42 -07:00
qctecmdr
08a7059080 Merge "arm: dma: Allow CMA pages to not have a kernel mapping" 2020-05-26 09:46:03 -07:00
qctecmdr
e9fb0680f4 Merge "msm: adsprpc: Fix NULL pointer error when DEBUG_FS is disabled" 2020-05-26 09:46:03 -07:00
qctecmdr
9db02bb1ad Merge "msm: rdbg: Add snapshot of remote debugger driver" 2020-05-26 09:46:02 -07:00
qctecmdr
89194b4b74 Merge "msm: kgsl: Use DMA APIs for cache operations" 2020-05-26 09:46:02 -07:00
qctecmdr
7dbb2a281f Merge "msm: cvp: handles dsp error more reliably" 2020-05-26 09:46:02 -07:00
Raghavendra Rao Ananta
c6146aa00d soc: qcom: socinfo: Add LAHAINAP's soc-id
Add "LAHAINAP", that has an msm-id of 439, to the list of
soc-ids supported.

Change-Id: I9e9a98bb66b541e654de6ad9e9a8ec9d2bd5cd03
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
2020-05-26 09:21:28 -07:00
qctecmdr
113813fd26 Merge "arm: make default iova alignment as 2mb" 2020-05-26 05:19:43 -07:00
Mohammed Nayeem Ur Rahman
9fb522a577 msm: adsprpc: Fix NULL pointer error when DEBUG_FS is disabled
Add extra checks to avoid NULL pointer derefernce when DEBUG_FS
is disabled.

Change-Id: I46ff3b8b27b53ff5bb5dead78ccdefc410435dda
Acked-by: Tadakamalla Krishnaiah <ktadakam@qti.qualcomm.com>
Signed-off-by: Mohammed Nayeem Ur Rahman <mohara@codeaurora.org>
2020-05-26 04:35:23 -07:00
qctecmdr
f32b8945f0 Merge "clk: qcom: camcc: Add support for CAMCC clock driver for SHIMA" 2020-05-26 01:31:01 -07:00
Mohammed Nayeem Ur Rahman
fac21defed msm: rdbg: Add snapshot of remote debugger driver
The Remote Debugger driver allows a debugger running
on a host PC to communicate with a remotestub running
on peripheral subsystems.
This snapshot was taken as of msm-3.10 commit
("Merge "msm: msm_bus: Provide valid input pointer argument").

Change-Id: Id79ca428b311dda90467155611af3e2a0fff1fcf
Acked-by: Devender Kaushik <dkaushik@qti.qualcomm.com>
Signed-off-by: Mohammed Nayeem Ur Rahman <mohara@codeaurora.org>
2020-05-26 12:50:12 +05:30
Raghavendra Rao Ananta
f1a4a49b2e aarch64: ABI: Remove slim_* APIs from whitelist
As the slim_* APIs are exported via a module that's enabled
in lahaina_GKI.config, they need not be whitelisted. Hence,
exclude them from the whitelist.

Change-Id: Idc10bed503b987710558d8bed32ab340afcef81d
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
2020-05-25 19:05:49 -07:00
Himateja Reddy
2a7519b146 msm: adsprpc: remove exsessive logging in context_free
Async RPC can easily exhaust the context table and results in failure.
Context free during context table exhaustion failure causes excessive
logging. Remove logging in context_free.

Change-Id: I4de2d638d465f98eeccabaefe99ae589e3780169
Signed-off-by: Himateja Reddy <hmreddy@codeaurora.org>
2020-05-25 18:57:01 -07:00
qctecmdr
729fffbd95 Merge "arm: dma_mapping: Support for DOMAIN_ATTR_S1_BYPASS attribute" 2020-05-25 06:14:50 -07:00
qctecmdr
4c41069d14 Merge "soc: qcom: spss_utils: fix driver module remove" 2020-05-25 06:14:50 -07:00
qctecmdr
81604f60ff Merge "coresight: tmc: set buffer size to 32MB on SW USB mode" 2020-05-25 06:14:49 -07:00
qctecmdr
54734c6f24 Merge "coresight: etm4x: call cpus_read_unlock in error exit" 2020-05-25 06:14:49 -07:00
qctecmdr
b6f208ddff Merge "clk: qcom: gcc-shima: Add support for ref clocks" 2020-05-25 06:14:48 -07:00
qctecmdr
8502acac7a Merge "input: touchscreen: st: fix security issue" 2020-05-25 02:30:40 -07:00
Patrick Daly
0b06cd5ca5 arm: dma: Allow CMA pages to not have a kernel mapping
Currently, there are use cases where not having any kernel
mapping is required; if the CMA memory needs to be used as
a pool which can have both cached and uncached mappings we
need to remove the mapping to avoid the multiple mapping
problem. Extend the dma APIs to use the DMA_ATTR_NO_KERNEL_MAPPING
with CMA. This doesn't end up saving any virtual address space
but the mapping will still not be present.

Change-Id: I64d21250abbe615c43e2b5b1272ee2b6d106705a
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:34:39 -07:00
Liam Mark
84df8c8f74 arm: dma-mapping: map_page map to nearest page
Since the page offset can be greater than the size of a page fix
arm_coherent_iommu_map_page so that it maps to nearest page
boundary.

This both prevents unnecessarily mapping memory we don't need to
map and fixes a issue where the unmap wasn't unmapping this extra
memory.

Change-Id: Iaa69aff7505ee75d1f2e69bb0cda814bc6211bd3
Signed-off-by: Liam Mark <lmark@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:34:25 -07:00
Shiraz Hashim
cdc7377df2 arm: dma-mapping: fix data types to hold size_t
size_t type data should not be held under variable of type
int, as this can truncate large values especially on a
64bit system. Fix it.

Change-Id: I5ad1ab321738772a99920e3fa287bda266cb05ed
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:28:24 -07:00
Shiraz Hashim
b7b349c452 arm: dma-mapping: DMA buf may not have cpu virtual addr
DMA buffers may not have cpu virtual addresses when
allocated using DMA_ATTR_NO_KERNEL_MAPPING attribute.
Page address should therefore be looked up while
searching for such dma bufs.

Also fix the printk format specifier to '%pK' to print
kernel pointers.

Change-Id: I5754cde63ace19aed88624a36186d012309d475b
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:27:55 -07:00
Charan Teja Reddy
bb7d10aa8e arm: make default iova alignment as 2mb
To get the 2MB aligned IOVA section mappings, set
ARM_DMA_IOMMU_ALIGNMENT to 9.

Change-Id: I3254c39e4864c32d6f25a4d416b1b7aec6756ecd
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:27:30 -07:00
Shiraz Hashim
61311e5672 arm: provision page alloc debug support
Equip arm to support ARCH_SUPPORTS_DEBUG_PAGEALLOC and
enable it by default.

Having this support means all pages freed at buddy level
would be marked as read-only and would help catch any
scribbling over free page area. Allocated pages mapping
attributes is restored to read/write.

ARCH_SUPPORTS_DEBUG_PAGEALLOC needs FORCE_PAGES which
ensures all kernel mapping are populated with page
granularity and it would ensure page level accesses  can
be rightly configured.

Change-Id: I9b23d1fb0b9594cc148b082c104da9a773c26057
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:26:24 -07:00
Shiraz Hashim
629471283e arm: mm: program ptes for access restriction
CONFIG_RODATA allows strict kernel mapping permissions to
be followed and accordingly maps regions as read-only,
not-executable etc. correspondingly. CONFIG_RODATA however
assumes all memory regions to be SECTION_SIZE aligned and
section mapped for performance reasons.

With CONFIG_FORCE_PAGES, we force all kernel mappings as
page mapped thus breaking CONFIG_RODATA.

Provide provision to apply permissions at page (pte)
level, if CONFIG_RODATA does not find section mapping.

Change-Id: I8dbf5c3741836bc63a231d8a471cf0306662993b
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:26:01 -07:00
Liam Mark
b4aefd26a7 arm: dma-mapping: handle IOVA address zero
The IOVA allocator used by these calls supports IOVA address
zero so properly handle IOVA address zero.

Change-Id: Iaaad45b42503f05f95d1333e010f6d8e3bdb1949
Signed-off-by: Liam Mark <lmark@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:25:21 -07:00
Chintan Pandya
832decaf00 arm: dma-mapping: map sg lists into the SMMU as virtually contiguous
In arm_iommu_map_sg, currently we map each individual link in the given
scatterlist into the SMMU individually such that they may or may not be
virtually contiguous.  However, in most of our use cases we
actually want the entire sg list mapped into the SMMU as a single
contiguous range.

This was missing for arm 32bit, add it.

Change-Id: Ibf67f29a60b8d19e526c4719590f2f473ea9dca5
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:24:44 -07:00
Laura Abbott
de79fc71ee arm: dma: Expand the page protection attributes
Currently, the decision on which page protection to use
is limited to writecombine and coherent. Expand to include
non consistent memory.

Change-Id: I7585fe3ce804cf321a5585c3d93deb7a7c95045c
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:23:08 -07:00
Shiraz Hashim
ae9f381057 arm: keep address range pmd aligned while remap
During early init, all dma areas are remapped to PAGE_SIZE
granularity. Since full pmd regions are cleared to be
remapped into PAGE_SIZE, ensure that address range is pmd
size aligned while not crossing memory boundaries.

This would ensure that even if address region is not pmd
aligned, its mapping would not be cleared but factored in to
PAGE_SIZE regions.

Change-Id: Iad4ad7fd6169cdc693d532821aba453465addb7c
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:22:49 -07:00
Shiraz Hashim
dd1e256440 arm: mm: consider only lowmem regions while remap
Consider only those memory blocks with lowmem while
remapping into 4KB regions using CONFIG_FORCE_PAGES
feature.

Change-Id: Ie209fce6c310f911d8cf02d977e226660684a6ab
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:11:18 -07:00
Shiraz Hashim
848bfb6423 arm: mm: fix pte allocation with CONFIG_FORCE_PAGES feature
CONFIG_FORCE_PAGES introduces a debug option to mark free
pages as read only in order to trigger a fault if any code
attempts to write to a page on the buddy list.

In order to achieve this it splits all section mappings in
to PAGE_SIZE pages during boot. While doing this split, it
wrongly allocates a pte (of page size) for each pmd. Linux
however in armv7 short descriptor format, uses same second
level pte for 2 consecutive pmds offset by the actual second
level table size. Refer comments in kernel file
arch/arm/include/asm/pgtable-2level.h for details.

Fix this by allocating pte for a section mapped pmd while
providing required offset if pte already exists.

Change-Id: Iadbaa5e71e4b220208a7275bf039a2a413349e42
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:10:57 -07:00
Laura Abbott
cec36b1c9c arm: Allow remapping lowmem as 4K pages
Lowmem is currently mapped with sections (1MB/2MB) whenever
possible due to TLB performance boosts. Sections cannot easily
be changed at runtime however which makes implementing certain
features annoying. Add an option to map lowmem with 4K patches.
This is intended to be used as a debugging feature and should
NOT be used for performance testing.

Change-Id: I9612a99b8e05a022f5ba7e568f21307cf66b5667
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Susheel Khiani <skhiani@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:10:39 -07:00
Qingqing Zhou
85b0f9f9f7 arm: dma-mapping: add dma mapper for io-pgtable-fast for 32 bit
io-pgtable-fast was implemented to achieve
better performance for IOMMU map/un-map. Add
DMA API support that goes through io-pgtable-fast
for 32 bit targets.

Change-Id: I3d0560a4331f6b7b87c70d0885df11d12cb1d6ec
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
[qqzhou@codeaurora.org: Reorganize codes to be more clear]
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-24 23:59:04 -07:00
Qingqing Zhou
020939113f arm: dma_mapping: Support for DOMAIN_ATTR_S1_BYPASS attribute
For iommus which do not use stage1 translation, stage2 may not be aware
of the device's dma_mask requirements. Choose the dma_ops such that
allocations are made within the dma_mask region and bounce buffers are
used as necessary.

Change-Id: I63ae3ff9e5ab608892d12db7a813264d234699ee
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-24 23:58:32 -07:00