Add config change to enable the rpm-smd driver for establishing
channel for APSS-RPM communication.
Change-Id: I858e97ed4f055eb874811e85f649d8a2e326c82e
Signed-off-by: Raghavendra Kakarla <rkakarla@codeaurora.org>
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Add support for new UFS PHY on SM8150 platform.
Change-Id: I8d28e798c080706280e0b55bcf474c3422985d2a
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
With fragmented physical memory, mappings are generated of lower granule.
This increases the unmap latency of large buffers. When not supporting
demand paging in smmu, unmap can defer the invalidation till next map.
This change aggregates invalidations across multiple unmaps till a new
mapping is created on that context. The new mapping can be using an iova
previously unmapped hence the stale TLB can cause issue. Hence invalidate
the TLB during map.
Change-Id: I1d64227ca075067a43075729ba26be684126d679
Signed-off-by: Prakash Gupta <guptap@codeaurora.org>
When a context bank's SCTLR is programmed for an SMMU client
that wishes to bypass S1 translations and enable io-coherency, the
SHCFG bitfield of the SCTLR is set to 0. This means that a
client's transaction's shareability memory attribute will not be
modified as it goes through the SMMU.
This is problematic if the SMMU client's transaction is marked as
non-shareable, as the attribute will not be modified to be classified
as io-coherent, since io-coherent transactions should be cacheable
and shareable. Instead, the transaction will not snoop the CPU
caches, and will go to DDR, and may read incorrect data.
Thus, program the SHCFG bitfield in the context bank's SCTLR to
override the shareability attribute to outer shareable when
enabling io-coherency for clients using S1 bypass.
Change-Id: Ia4c1bbe7812ce7c2062c636e2b1bb39fa1ac516c
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
The reference clock source is used when switching
the pipe clock mux to XO before turning off gdsc.
Change-Id: I7861c1ae6dded2cc79e796b22e766c54aef1d461
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
When running concurrent iptables rules replacement with data, the per CPU
sequence count is checked after the assignment of the new information.
The sequence count is used to synchronize with the packet path without the
use of any explicit locking. If there are any packets in the packet path
using the table information, the sequence count is incremented to an odd
value and is incremented to an even after the packet process completion.
The new table value assignment is followed by a write memory barrier so
every CPU should see the latest value. If the packet path has started with
the old table information, the sequence counter will be odd and the
iptables replacement will wait till the sequence count is even prior to
freeing the old table info.
However, this assumes that the new table information assignment and the
memory barrier is actually executed prior to the counter check in the
replacement thread. If CPU decides to execute the assignment later as there
is no user of the table information prior to the sequence check, the packet
path in another CPU may use the old table information. The replacement
thread would then free the table information under it leading to a use
after free in the packet processing context-
Unable to handle kernel NULL pointer dereference at virtual
address 000000000000008e
pc : ip6t_do_table+0x5d0/0x89c
lr : ip6t_do_table+0x5b8/0x89c
ip6t_do_table+0x5d0/0x89c
ip6table_filter_hook+0x24/0x30
nf_hook_slow+0x84/0x120
ip6_input+0x74/0xe0
ip6_rcv_finish+0x7c/0x128
ipv6_rcv+0xac/0xe4
__netif_receive_skb+0x84/0x17c
process_backlog+0x15c/0x1b8
napi_poll+0x88/0x284
net_rx_action+0xbc/0x23c
__do_softirq+0x20c/0x48c
This could be fixed by forcing instruction order after the new table
information assignment or by switching to RCU for the synchronization.
Change-Id: I41ffb931b711cd2de9896d9ca7f13dda79e6709f
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
In scenario where channel shutdown is in progress interrupt
handler can call callback for mbox channel which might be
free.
Change to avoid race between mbox channel free and receive
data.
Change-Id: I07ef5f08aa1946be775de6b3e2f89d9069fa6ee3
Signed-off-by: Mayank Grover <groverm@codeaurora.org>
defconfigs generated at runtime scan through dependency order of
config fragments and enable respective config flag. Remove duplicate and
unnecessary configs in debug config fragment.
Change-Id: Ifbc74382a16479e0b7de068fe9c92211f49c1c92
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
The IPC log context and the log buffers allocated
are not destroyed upon remove, this will lead to
memory leak and cause memory allocation failures,
if the probe fails indefinitely.
Change-Id: I6844507cb5c5bec4908f34b3f00090594d2cefcf
Signed-off-by: Sriharsha Allenki <sallenki@codeaurora.org>
Add config flag to enable tzlog driver on sdxlemur.
Change-Id: I188241dc44e808ac00003eadefe76a11dd37f770
Signed-off-by: Anmolpreet Kaur <anmolpre@codeaurora.org>
Add config flag to enable qcrypto, qcedev and
qce drivers on sdxlemur.
Change-Id: Id21a6135d0763fbfa371ff4c11749943cba34373
Signed-off-by: Anmolpreet Kaur <anmolpre@codeaurora.org>
Add clock IDs for GCC and clients to be able to request
for clocks from these clock controllers.
Change-Id: Ib6de5e51c0561650d2942817fbe1b1a6c3fb5424
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add support for RPM-SMD and PMIC clocks for sdxnightjar
which are required for the clients to enable/disable.
Change-Id: Ic65ffed06fc5fa070f6ce1ed2da033899a4dd00b
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add snapshot of virtio regulator driver from msm-4.14.
This snapshot is taken as of msm-4.14 commit 26888d5a6921
("regulator: virtio: wait for backend response forever").
Change-Id: Iff5ec67f7918df08c939f4ea398d455012187b71
Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
The 8 x 8 JSC MCP part has 2 x 4Gbit NAND dies from Hynyx and
supports ONFI. But ONFI parameter page field values below read from the
device only account for 4Gbit instead of 8Gbit:
Pages/Block : 64
Page size : 4096
num_blocks_per_unit : 2048
num_units : 1
JSC vendor has no plans to “correct” the ONFI parameter page
field values in their current and future 8 x 8 MCP parts to properly
identify the NAND device size as 8Gbit.
Using Read ID values (manufacture ID (0xAD), device ID(0xA3)) instead to
identify the part and multiplying the density to identify the part as
8Gbit device size.
Change-Id: Id900f3475e68740597fbc4e6decb1b7920f09c57
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
Following flags are needed to support block crypto
based inline encryption framework on EMCC devices:
1. CONFIG_MMC_CQHCI_CRYPTO.
2. CONFIG_MMC_CQHCI_CRYPTO_QTI.
Test:
1. Device booted upto UI with File Based Encryption enabled.
2. Key insertion using fscryptctl tool.
3. Created new files under /data and checked retention across
multiple re-boots.
4. vts_kernel_encryption_test tests.
5. check_encryption test for verifying metadata encryption.
Change-Id: I574838b0e65e336d2c056ab7cfce8c9cd3e801e0
Signed-off-by: Vaibhav Agrawal <vagrawa@codeaurora.org>
store eth_ready_info pointer for late callback
trigger instead of storing cb and user data addresses.
eth_ready_info pointer is static and shall be searched
when callback is unregistered.
Change-Id: I03cbbc4920ee663890bad12ece6d41e9bd2a68d5
Signed-off-by: Amir Levy <alevy@codeaurora.org>
On A660 GPU, PWR_COL_PREEMPT_KEEPALIVE register is used to disallow
ifpc during preemption trigger. Dump this register also in case of
wait for lowest idle timeout to capture this ifpc abort reason.
Change-Id: Ide6bef3169987f17ec6a761e9735caef1c5deaa7
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
Jann spotted the security hole due to race of mm ownership check.
If the task is sharing the mm_struct but goes through execve() before
mm_access(), it could skip process_madvise_behavior_valid check. That
makes *any advice hint* to reach into the remote process.
This patch removes the mm ownership check. With it, it will lose the
ability that local process could give *any* advice hint with vector
interface for some reason (e.g., performance). Since there is no
concrete example in upstream yet, it would be better to remove the
abiliity at this moment and need to review when such new advice comes
up.
Change-Id: I536de5167b6cf7378a06a6b7815f1dd2869a56a4
Fixes: ecb8ac8b1f14 ("mm/madvise: introduce process_madvise() syscall: an external memory hinting API")
Reported-by: Jann Horn <jannh@google.com>
Suggested-by: Jann Horn <jannh@google.com>
Signed-off-by: Minchan Kim <minchan@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Git-Commit: a68a0262abdaa251e12c53715f48e698a18ef402
Git-Repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
KGSL needs to enable apb_pclk for QDSS register access.
Add apb_pclk to the clock list. Increment KGSL_MAX_CLKS
to support apb_pclk.
Change-Id: I017628ddda2b5807aab4d8970a4ceab2d9174f53
Signed-off-by: Harshitha Sai Neelati <hsaine@codeaurora.org>
- This change will add sfe support for the target
Change-Id: I0088f2d64fbf2ebb10435138edcca0eb9ddb0f4b
Signed-off-by: Aman Gupta <amangupt@codeaurora.org>
