Commit graph

893,362 commits

Author SHA1 Message Date
Wu Gao
87b8807966 cnss2: Avoid to reject suspend pci for non DRV connected platform
For no DRV connected platform, it will reject to suspend pci since
DISABLE_DRV bit isn't set. So check both flags firstly before suspend
pci.

Change-Id: Ifc3de23def6537165f69dd6ca07da9f57f136607
Signed-off-by: Wu Gao <wugao@codeaurora.org>
2021-01-07 22:33:31 +08:00
Jagadeesh Kona
05e05d692f clk: qcom: debugcc-yupik: Update all PCIE clocks to measure only
PCIE clocks are not controlled from HLOS in YUPIK. But in order
to measure them from HLOS, update all PCIE clocks to measure only.

Change-Id: I8749032c187694bb57bf89feccf129fd4c6b7299
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
2021-01-07 16:23:19 +05:30
Naina Mehta
67d881e295 driver: pinctrl: Add reserved GPIOs for Yupik
Certain GPIOs are reserved for secure world and cannot be accessed by HLOS.
Supply "reserved_gpios" to msm_pinctrl to mark these pins as invalid.

Change-Id: I7ff8444af2819a68c60e66bd4e4e9f5ecf4990fa
Signed-off-by: Naina Mehta <nainmeht@codeaurora.org>
2021-01-07 00:05:42 -08:00
Bhaumik Bhatt
85a71cb100 bus: mhi: core: Address pending BW requests for legacy mode
It cannot be guaranteed that certain legacy mode controllers stay
in M0 while a BW request is being processed. Ensure that those
pending BW requests are addressed when M0 entry occurs after a BW
request is processed but not responded to.

Change-Id: I6132116fae76fa10477aa7061c24f3ff5ac60a34
Signed-off-by: Bhaumik Bhatt <bbhatt@codeaurora.org>
2021-01-06 18:05:33 -08:00
Ritesh Kumar
bd5377681e input: touchscreen: nt36xxx: Expose trusted touch event
Expose trusted touch event through sysfs node for TUI
error handling.

Change-Id: Ib303d36e3b807c770f670abc2a2ee3e3fd2e009d
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
2021-01-06 13:17:18 -08:00
Ritesh Kumar
c30aa8dbe9 input: touchscreen: nt36xxx: Block resume work on PVM
While trusted touch is underway, block resume work
to flush touch FIFO since ownership of register space
is with Trusted VM.

Change-Id: Ib87a81aa8f39631ae3f3ea44f4a5dee4563bc514
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
2021-01-07 02:46:49 +05:30
Ritesh Kumar
96ea71a1c2 input: touchscreen: nt36xxx: release i2c session early
Release I2C session lock before releasing IO regions in TVM
during trusted touch scenario.

Change-Id: Ibd3b63e5d084097eb464e3697b8d7d82ea17262e
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
2021-01-06 12:42:26 -08:00
Ritesh Kumar
27da55afee arm64: defconfig: Enable novatek trusted touch for genericarmv8
Enable Trusted touch config in genericarmv8 defconfig for
novatek touch driver.

Change-Id: Ic96ec1971314479ed809c1d3b403237c258a7e5f
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
2021-01-06 12:42:18 -08:00
Ritesh Kumar
cccc78c256 arm64: defconfig: Enable novatek trusted touch on lahaina
Add trusted touch support to Lahaina GKI defconfig for
novatek touch driver.

Change-Id: I7da16992f20fee569f2b8da583543338ad3175d8
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
2021-01-06 12:42:11 -08:00
Ritesh Kumar
36f6aedb51 input: touchscreen: nt36xxx: Add trusted touch support
Add Trusted touch support to nt36xxx Touchscreen driver.
This feature enables driver to operate in trusted touch
mode in trusted virtual machine(TVM). The primary virtual
machine(PVM) lends resources such as IO memory and touch
irq to TVM prior to trusted touch is initiated and
reclaims those resources back after trusted touch usecase
finishes. The resource requirements of TVM such as clock,
regulators etc are taken care by PVM. Introduce state
machine for various checkpoints in trusted touch usecase.
In error scenarios, this state machine helps driver to
rollback to previous state.

Change-Id: I5000ba016cee21c7b6b6beab8a7bb15a8c23f8d5
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
2021-01-06 12:42:01 -08:00
Jagadeesh Kona
920c63faca arm64: defconfig: Add support for DISPCC and debugCC for YUPIK
Enable Display and debug clock controllers for YUPIK.

Change-Id: I1d458d091c57011f6e9780956769051b4760eb18
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
2021-01-07 01:38:45 +05:30
Jagadeesh Kona
f1a099474f clk: qcom: debugcc: Add debug clock controller support for YUPIK
Add debug clock controller to support measure functionality for
all clock controllers.

Change-Id: I45d097d077c50efcde3d4a31b3b601deab9c1059
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
2021-01-07 01:38:35 +05:30
Jagadeesh Kona
8b82fcc32c clk: qcom: dispcc: Add display clock controller for YUPIK
Add the display clock controller to support display port
related branches, PLLs and RCGs.

Change-Id: I3b9c15e1eab364250300d1ff9121285a044ced2e
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
2021-01-07 01:00:45 +05:30
Shreyas K K
b3c4d2fb9e defconfig: gen3auto: Enable service locator and notifier
Enable service locator and service notifier on gen3auto.

Change-Id: Ida4e037808c50fca8096fba8d24e16c5a4af6bb3
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
2021-01-06 13:04:41 +05:30
Shreyas K K
d843632ad7 defconfig: gen3auto: Enable PIL & SSR drivers
Enable PIL, SSR and related drivers to load firmware
images for other subsystems and send out notifications
about subsystem states.

Change-Id: Ic85175ddf17486e21427dc1c8540b8016ca6aa9e
Signed-off-by: Vivek Kumar <vivekuma@codeaurora.org>
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
2021-01-06 13:02:55 +05:30
Neeraja P
9d5f8de63c msm: kgsl: Deregister gpu address on memdesc_sg_virt failure
When memdesc_sg_virt returns error in kgsl_setup_anon_useraddr function,
the gpu address registered in SVM region will not be deregistered.
This change deregisters the gpu address on memdesc_sg_virt failure.

Change-Id: Ic99167e283a0c6331bb9f5f0b608b6cdb3c918e4
Signed-off-by: Neeraja P <neerp@codeaurora.org>
2021-01-06 10:46:19 +05:30
Zhao, Yuan
6f77167907 clk: qcom: check for change in RCG configuration during set_rate
For DSI byte clock RCG, check if there is a change in existing
settings before updating RCG configuration. This is needed to
avoid glitch on the display panel when there is a change in the
DSI byte clock frequency with display enabled.

Change-Id: I8ef0331cbb466b399cd12199b4d335ed44997dbc
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Zhao, Yuan <yzhao@codeaurora.org>
2021-01-05 18:50:18 -08:00
David Collins
95d95d5a31 regulator: rpmh-regulator: fix rpmh_regulator_init_vreg_supply memory leak
Commit 29c41d5c47 ("regulator: rpmh-regulator: support parent
supply specification in subnodes") introduced a memory leak in
the function rpmh_regulator_init_vreg_supply() due to 'buf' not
being freed in the new 'else if' statement.  Fix this memory leak
by freeing 'buf' correctly.

Change-Id: If2748b595d8ae3a4564a2956a67aeda476975309
Signed-off-by: David Collins <collinsd@codeaurora.org>
2021-01-05 11:18:13 -08:00
Harshdeep Dhatt
9f96936918 msm: kgsl: Vote for l3 via icc_set_bw
Henceforth, l3 clock is scaled using icc api instead
of the clock api.

Change-Id: I0de3250ed402b940dfb5991ea837edb98734529a
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2021-01-05 11:54:20 -07:00
Harshdeep Dhatt
eef17de50b msm: kgsl: Set DDR qos level based on GPU bus IB vote
For the highest IB vote, enable DDR qos level which increases
performance by disabling certain DDR low power states.

Change-Id: Iaabc99f724ca6f2b8de2a95da00f73608209e97f
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
2021-01-05 11:54:19 -07:00
qctecmdr
4afb66961f Merge "spi: spi-msm-geni: Configure DFS index and clk before doing set rate" 2021-01-05 10:50:55 -08:00
qctecmdr
08dc7ff311 Merge "spi: spi-msm-geni: Calculate transfer timeout dynamically" 2021-01-05 10:50:54 -08:00
qctecmdr
14d5ad2a5e Merge "arm: vdso: Fix GENERIC_GETTIMEOFDAY dependencies" 2021-01-05 10:50:54 -08:00
qctecmdr
50694617b0 Merge "scsi: ufs: Increase the PA_HIBERN8TIME on the host" 2021-01-05 10:50:53 -08:00
qctecmdr
77aca605c0 Merge "clk: qcom: gcc: Add support for GCC clock Driver for sdxnightjar" 2021-01-05 10:50:53 -08:00
qctecmdr
a704da9e6e Merge "clk: qcom: cpu: Re-org CPU clock driver for SDXLemur" 2021-01-05 10:50:52 -08:00
Lakshit Tyagi
776f497b38 net: aquantia: Adding IPA glue layer
Add IPA offload feature for Aquantia.

Change-Id: Ibf8ae4fb708f97881fdd9e5e796fe7812241c8cc
Signed-off-by: Lakshit Tyagi <ltyagi@codeaurora.org>
2021-01-05 08:48:40 -08:00
qctecmdr
1975f8264d Merge "cnss2: skip pci link recovery for EACCES error" 2021-01-05 06:05:14 -08:00
qctecmdr
901012883c Merge "arm64: defconfig: explicitly SLIMBUS_MSM_NGD as m" 2021-01-05 06:05:13 -08:00
qctecmdr
82ffd15f1b Merge "arm64: Kconfig: Add config option for SA6155" 2021-01-05 06:05:13 -08:00
qctecmdr
5d3347b4b6 Merge "firmware: qcom_scm: Check for NULL before dereferencing __scm" 2021-01-05 00:35:26 -08:00
qctecmdr
b8aa4abaea Merge "mmc: core: Retry claim host in mmc_sd_detect" 2021-01-05 00:35:25 -08:00
qctecmdr
bf525affe2 Merge "input: touchscreen: focaltech: Block resume work on PVM" 2021-01-05 00:35:25 -08:00
qctecmdr
a92909e0b4 Merge "input: touchscreen: st: Block resume work on PVM" 2021-01-05 00:35:25 -08:00
qctecmdr
9c5eac7747 Merge "coresight: Add snapshot of Coresight Dbgui driver" 2021-01-05 00:35:24 -08:00
qctecmdr
d84c33524e Merge "arm64: defconfig: Enable LLCC driver" 2021-01-05 00:35:24 -08:00
qctecmdr
39b1e4e2e5 Merge "asoc: Update supported rate and format for dummy dai" 2021-01-05 00:35:24 -08:00
qctecmdr
7bd2a2072a Merge "usb: gadget: composite: Add spinlock protection for usb string descriptor" 2021-01-05 00:35:23 -08:00
Shyam Kumar Thella
7f65227406 iio: qcom-spmi-adc5: Fix HW settle time table naming for ADC5 lite
Correct the hw_settling times array defined for ADC5 lite.

Change-Id: I38eee9b3f76cb40e286f9e7e3fbf296b3f3ccfe5
Signed-off-by: Shyam Kumar Thella <sthella@codeaurora.org>
2021-01-05 12:48:30 +05:30
Rishabh Bhatnagar
7bbba81366 devfreq: memlat: Fix macros to support 32 bit kernels
Cast MBYTE macro to unsiged long instead of unsigned long long.
Unsigned long long causes division errors when used for 32 bit
kernels. Also, add a new macro for Mbps to icc conversion
without loss of precision.

Change-Id: I584869c510d614e47ab7090a1f328df307d412a8
Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
2021-01-04 17:50:39 -08:00
Rishabh Bhatnagar
bd14317182 devfreq: memlat: Move hp_restart_events within the HOTPLUG ifdef
To compile for targets where HOTPLUG is disabled move the
msm_hp_restart_events function within the HOTPLUG ifdef code.

Change-Id: If316b76812dd8e3f45a73fe1d4f908b5ffabeef4
Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
2021-01-04 17:30:39 -08:00
Paras Singh Jain
eb11987e63 netfilter: contrack: Null pointer check is added
Prior to null pointer check, SIP node was deleted from the list
a null pointer check is added to confront the exception.

Change-Id: Ia12fa468eed7d1a91fad96840fa27cb0e4e208a8
Acked-by: Vinisha Varre <vvarre@qti.qualcomm.com>
Signed-off-by: Paras Singh Jain <parassin@codeaurora.org>
2021-01-05 05:01:38 +05:30
Raghavendra Rao Ananta
c75011c99d arm: vdso: Fix GENERIC_GETTIMEOFDAY dependencies
GENERIC_GETTIMEOFDAY can be enabled only if HAVE_GENERIC_VDSO
is enabled. However, HAVE_ARM_ARCH_TIMER selects it unconditionally,
thus throwing the following warning:

WARNING: unmet direct dependencies detected for GENERIC_GETTIMEOFDAY
Depends on [n]: HAVE_GENERIC_VDSO [=n]
Selected by [y]:
- HAVE_ARM_ARCH_TIMER [=y] && CPU_V7 [=y]

Fix this by selecting GENERIC_GETTIMEOFDAY conditionally in
HAVE_ARM_ARCH_TIMER as well.

Also, handle this conditional dependency in all the references.

Change-Id: Iccb154ad4c0f49857115372334e49504f31a8380
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
2021-01-04 12:57:15 -08:00
Ashok Vuyyuru
cceceac1d8 firmware: qcom_scm: Check for NULL before dereferencing __scm
The function qcom_scm_mem_protect_region_id dereferences __scm without
checking for NULL and could potentially lead to a NULL pointer exception.
This scenario can happen if the clinet calls qcom_scm_mem_protect_region_id
before qcom_scm driver is even probed. Hence, check for NULL before
dereferencing it.

Change-Id: I1a9eba6d45ba8ebf73da80bca984b4dfad05042e
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
2021-01-04 20:56:54 +05:30
Sarthak Garg
94361fce31 mmc: host: sdhci-msm: Don't return error on missing bus voting paths
On MDM targets we have only one path for bus voting (sdhc-ddr).
If we provide only one path and not the other one then probe will
itself fail as per the current logic.

Don't return error when bus voting paths not found.

Change-Id: Idf5401266793f4d4003391816f7511f8c0754696
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
2021-01-04 18:57:33 +05:30
Sarthak Garg
4b432d2057 defconfig: Enable SD card related configs for sdxnightjar
Enable configs required for SD card support on sdxnightjar.
Also enable the required Block layer configs.

Change-Id: I01d077c9d6218da11b503592bcee302db8e3eb44
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
2021-01-04 18:31:20 +05:30
Neeraj Upadhyay
87fa6c04a8 arm64: defconfig: Enable LLCC driver
Enable the Last Level Cache Controller (LLCC) driver for Yupik.

Change-Id: I31723ec8588d398d22d0fbcf69ca0425dbb423f6
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
2021-01-04 18:07:21 +05:30
Ziqi Chen
06efe84d5f scsi: ufs: Increase the PA_HIBERN8TIME on the host
The device advertises PA_HIBERN8TIME may not be enough for some UFS
devices. To workaround this issue, host should add more 100 us.

The commit 8941234ea1 ("scsi: ufs: Add UFS_DEVICE_QUIRK_PA_HIBER8TIME
quirk") just increase PA_HIBERN8TIME base on TX_HIBERN8TIME_CAPABILITY,
we should increase PA_HIBERN8TIME directly because the
RX_HIBERN8TIME_CAPABILITY may be more than TX_HIBERN8TIME_CAPABILITY.

Change-Id: If5e28e11a656df999fc50014e65bc89498b28499
Signed-off-by: Ziqi Chen <ziqichen@codeaurora.org>
2021-01-04 17:33:58 +08:00
Yuanfang Zhang
57e094d312 coresight: Add snapshot of Coresight Dbgui driver
Add snapshot for coresight Dbgui driver from msm-3.18
commit cf126d1be1a("ANDROID: sdcardfs: Add option to
not link obb"). Make necessary change to adopt coresight
framework change.

Change-Id: I3cf911f20b79f88cbc6482304fd6f43989aa881a
Signed-off-by: Yuanfang Zhang <zhangyuanfang@codeaurora.org>
2021-01-04 16:01:48 +08:00
Rakesh Kota
3b29f87982 clk: qcom: gcc: Add support for GCC clock Driver for sdxnightjar
Add MSS_Q6_BIMC_AXI and MSS_CFG_AHB clocks to GCC for peripheral
clock clients to be able to request for the clocks. While at it, also
add support for debug clock controller to measure frequency of clocks.

Change-Id: Iefdd56797632c317c8ae31c277380622726a9c7c
Signed-off-by: Rakesh Kota <kotarake@codeaurora.org>
2021-01-04 11:35:43 +05:30