ARM cannot natively read 64-bit address. As such the readq_ variants
are not defined for this architecture. Add a 32-bit equivalent to read 2
sequential 4-byte memory into a u64 value. Let's keep them locally
defined for now, since they are not native to the ARM architecture.
Change-Id: I9d00d0a9cd185e658d7b860cac2f59c8438e1b30
Signed-off-by: Raghavendra Kakarla <rkakarla@codeaurora.org>
Add support for qcom_clk_dump and qcom_clk_bulk_dump API's
which can be used by the clients to dump the registers
associated with the clock and it's parents.
Change-Id: Iea7f30bb4e789e41dbae41b88514ffd53c136174
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
New dedicated pipe definition for LE MHI use cases.
Change-Id: I7426de281a172fac221605c7344d8f6c6e6c107d
Signed-off-by: Armaan Siddiqui <asiddiqu@codeaurora.org>
Add support for monaco pin configuration and control
via pinctrl framework.
Change-Id: I88b348eb4018d57484c2f8d154aeb3090b2b1a75
Signed-off-by: Nagireddy Annem <nannem@codeaurora.org>
Add support for WARN_CLK to dump the clock registers and
calltrace in case of failure in the kernel message.
Change-Id: If7452aaa02cc50deafd6f3721921f66cad9ab932
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add ADDR_MODE_CNTL registers for HLSQ, SP, TPL1 for legacy snapshot for
holi gpu to dump registers from the host driven path. This will help to
read value of addr_mode_cntl for these blocks when crash dumper is not
used or it is timed out.
Change-Id: Id1898883aa59c97ed61e616b5a4a2e744c35292b
Signed-off-by: Indira Biruduraju <ibirudur@codeaurora.org>
Propagate a change from 4.19 to 5.4 for SPI. 'commit 556e7c13ceaa
("spi: spi-msm-geni: Clear the RX fifo if FIFO has data after timeout")'.
Change-Id: Ica785f7b3cd3a9f9df6d173413ce136c2a018312
Signed-off-by: Vipin Deep Kaur <vkaur@codeaurora.org>
Support to dump PARF,PHY,DBI/dm_core registers
for PCIe linkdown.
Change-Id: I54a19245e91e68f0d58f230509e6cb1a2ff02665
Signed-off-by: Vivek Pernamitta <vpernami@codeaurora.org>
Add debug enhancement logs to notify request timeout, when cqe is
turned off and when deferred scaling happens.
Change-Id: Ib499f41632427cba3ab0b67e04d605b6cf4419f5
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Add a check for valid vmids before doing an allocation
for msm system heap. This check does a hyp_assign on a
page, stores the vmids and mark them as valid or invalid
based on hyp_assign result. If vmid is invalid it returns
or if its valid then proceeds with the allocation. So, this
prevents ion pages leak in cases where hyp_assign fails.
Also add a check for ion_hyp_assign_sg return value to
prevent leak.
Change-Id: Ibbc150490daf69d27b36db0e45a3c58496e6b9bd
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
carve out frequency boost functionality of msm_perf driver
and enable it on non perf images too.
Change-Id: I2a0af988edf04a88d2fc16018f50830a0ab73220
Signed-off-by: Kishore Sri venkata Ganesh Bolisetty <bsrivenk@codeaurora.org>
iommu_dma_map_sg() attempts to perform cache maintenance with
iommu_dma_sync_sg_for_device() prior to mapping the scatter gather
list to an IOVA. iommu_dma_sync_sg_for_device() uses the DMA address
in the scatter gather list structure to determine if the buffer is
mapped as cached or uncached by invoking iommu_is_iova_coherent().
Since the buffer has not been mapped yet, the DMA address in the scatter
gather list structure will be 0. If IOVA 0 is not mapped in the client's
IOMMU page tables, then iommu_is_iova_coherent() will return false,
and cache maintenance will be performed on the buffer, even for clients
that are io-coherent, which is not correct, as no cache maintenance is
required for io-coherent clients.
Ensure cache maintenance happens only after the buffer has been mapped,
so that iommu_dma_sync_sg_for_device() can correctly determine if
cache maintenance is required.
Change-Id: Ie1cec69077eaeada00b5a2709b6d1680afdaaeba
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
For security reasons, allow modifying register values via the regmap
debugfs interface only on debug builds.
Change-Id: Ie22dbb2ff72da2072d46ab1116fb9623fe2185ff
Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org>
Euro headset is sometimes detected as headphone post PDR.
This is due to race condition between powering up of PGA
and cross connection detection due to which cross conn
detection is not successful resulting in usb analog headset
being detected as headphone post PDR. Save switch_control
value before PDR and apply same value during fsa reg notifier
after PDR so that euro side does not detect as cross conn
post PDR to resolve issue.
Change-Id: I4af17d83a8e4a55185421b370162d8e7a5d5b91f
Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
Add master and slave ID constants for all Qualcomm Technologies, Inc.
SM8150 interconnect providers which consumers can use to set bandwidth
constraints and find paths in the NoC (Network-On-Chip) topology.
Change-Id: Ie3d92159bf34e2cd57873cd3cd85c75e6a62638a
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
Drivers supporting 4096-QAM rates as a vendor extension in HE mode need
to update the correct rate info to userspace while using 4096-QAM (MCS12
and MCS13) in HE mode. Add support to calculate bitrates of HE-MCS12 and
HE-MCS13 which represent the 4096-QAM modulation schemes. The MCS12 and
MCS13 bitrates are defined in IEEE P802.11be/D0.1.
In addition, scale up the bitrates by 3*2048 in order to accommodate
calculations for the new MCS12 and MCS13 rates without losing fraction
values.
CRs-Fixed: 2796770
Signed-off-by: Vamsi Krishna <vamsin@codeaurora.org>
Signed-off-by: Jouni Malinen <jouni@codeaurora.org>
Link: https://lore.kernel.org/r/20201029183457.7005-1-jouni@codeaurora.org
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Git-commit: 9c97c88d2f4b221d99491c3196da42004c195fb5
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
Change-Id: I44f71f40a57b57703bbbe138e690d6f92369d0ec
Signed-off-by: Vamsi Krishna <vamsin@codeaurora.org>
