Commit graph

1,818 commits

Author SHA1 Message Date
qctecmdr
65c84a87ee Merge "disp: msm: sde: perform cmd encoder disable only for master" 2021-01-05 00:59:32 -08:00
Andhavarapu Karthik
d92bb74dfd disp: msm: sde: add rev check for mdp in yupik target
Add required revision checks for mdp in yupik target.

Change-Id: I2747a0addfb3b4880397d56b18a9e9aa9644df34
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
2020-12-31 16:45:40 +05:30
Raviteja Tamatam
49e09fde9d disp: msm: sde: perform cmd encoder disable only for master
In dual DSI cases sde_encoder_helper_phys_disable needs to be
called only for master encoder.

Change-Id: If2d327a4800914fe365c6877bf7854275a4434ae
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
2020-12-28 18:50:25 +05:30
qctecmdr
8acd9ca084 Merge "display: msm: sde: update qos lut after scaler config" 2020-12-21 19:51:34 -08:00
qctecmdr
71d4e079bf Merge "disp: msm: dp: log the dp mst connector id information" 2020-12-21 10:09:14 -08:00
Abhijit Kulkarni
80bf89b836 display: msm: sde: update qos lut after scaler config
This change moves the code of updating the qos lut for qseed3
to each plane after updating the scaler configuration. This
avoids using stale values for qos settings.

Change-Id: I2c55a98e1ba9790d596c55160933cd5afd2388e5
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-12-21 09:38:38 -08:00
qctecmdr
91d1ed8e79 Merge "disp: msm: dsi: avoid debugfs HW access based on HW ownership" 2020-12-21 04:42:30 -08:00
Sankeerth Billakanti
c6d5c4d121 disp: msm: dp: log the dp mst connector id information
Logging connector id will help debug the issues related to
DP MST stability and pre-merge tests. This change will log
the DP MST connector IDs modified during stability tests.

Change-Id: Ifaf8e319697a809b02c24c473acec8da521286e2
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
2020-12-20 14:30:14 +05:30
qctecmdr
eb21ca8701 Merge "disp: msm: sde: add scaler3_cfg and pixel_ext to sde plane" 2020-12-18 12:26:56 -08:00
Veera Sundaram Sankaran
35d1cdafd9 disp: msm: dsi: add stub function parse power_cfg in trusted-vm
In trusted-vm, there are no power cfg entries in device-tree as
there is no support. Add stub function to avoid parsing errors
related to power cfg in trusted-vm.

Change-Id: Id28ad9a4d5608d561e22b318a08c6bc1ccc5f2ee
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-12-17 15:28:04 -08:00
Veera Sundaram Sankaran
8f95751727 disp: msm: dsi: avoid debugfs HW access based on HW ownership
Add VM ownership checks before accessing the HW through the debugfs
path in dsi display/ctrl modules to avoid illegal access.

Change-Id: Ia6e2ab0ef60d0f11e5945a63885d939db2ef78b0
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-12-17 15:23:03 -08:00
Veera Sundaram Sankaran
4c29eaf3b0 disp: msm: avoid sde_dbg HW access based on HW ownership
Add VM ownership checks before accessing the HW through the debugfs
path in sde dbg module to avoid illegal access. Set the ownership
status on bootup based on the VM.

Change-Id: I30f2a1eb7e049740f1f7fe3ed03aa411264ba7b3
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-12-17 15:23:03 -08:00
Veera Sundaram Sankaran
3c1c4cd333 disp: msm: sde: avoid sde debugfs register access based on HW ownership
Add VM ownership checks before accessing the HW through the debugfs
path in sde crtc/encoder/connector modules to avoid illegal access.

Change-Id: I4ff8f29353835d263beb2091bdeec40125addbf8
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-12-17 15:23:03 -08:00
Rajeev Nandan
4060bdee77 Revert "disp: msm: dsi: move backlight operations to post kickoff"
This reverts commit e60959b052.

Change-Id: I539522a6a01297fecfafb446a44e725679bc39c0
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
2020-12-15 18:06:04 +05:30
Xiaowen Wu
1661be9086 disp: msm: sde: add scaler3_cfg and pixel_ext to sde plane
Add scaler3_cfg and pixel_ext to sde plane to avoid updating state
variables in commit thread. This fixes atomic check failure when
scaler lut is not set.

Change-Id: I936b124ca6f90af22a87df31536204e837422a70
Signed-off-by: Xiaowen Wu <wxiaowen@codeaurora.org>
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-12-14 12:41:13 -08:00
qctecmdr
554a3b8b06 Merge "disp: msm: dp: validate edid before dereferencing" 2020-12-14 09:56:07 -08:00
qctecmdr
e0695d4236 Merge "disp: msm: sde: cleanup ctl/intf registers on cmd encoder disable" 2020-12-12 22:39:19 -08:00
qctecmdr
93331df7d7 Merge "disp: msm: dsi: enable DMA cmd scheduling for video mode panels" 2020-12-11 09:49:33 -08:00
Rajeev Nandan
e60959b052 disp: msm: dsi: move backlight operations to post kickoff
This change moves the backlight update operation from
drm bridge enable to connector post kickoff.

When timing engine is enabled with programmable fetch
enabled, the timing engine will start counting from
the prog_fetch_start point (which is somewhere in VFP).
It’s a grey area from that point to the actual panel
vsync and SW should not trigger DMA command during that
time.

During display resume, sometimes the INTF timing engine
do not get enabled completely at the first vblank irq.
The backlight update cmd transfer trigger as part of the
drm bridge enable can also take place at the same time,
that may cause DSI cmd transfer failure.

Change-Id: I2722d3c23012ef0e7bcc7f728ec5658318ce4e60
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
2020-12-11 12:14:54 +05:30
Veera Sundaram Sankaran
030e3f15a7 disp: msm: sde: cleanup ctl/intf registers on cmd encoder disable
The SDE RM determines the number of displays enabled in cont-splash by
checking the INTF_ACTIVE bits in the ctl. The trusted-vm relies on the
same cont-splash path during transitions and the stale ctl INTF_ACTIVE
on dual display usecases leads to wrong status check. Currently, only
video/wb encoders use the phys_encoder disable helper during encoder
disable to clear out few ctl/intf registers. Extend it for cmd encoder
as well to remove the stale entries.

Change-Id: I7f21ef46178ce3943ee85abdf29f7cdef93d7c52
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-12-10 18:37:34 -08:00
Rajeev Nandan
37b2f80ad4 disp: msm: dsi: enable DMA cmd scheduling for video mode panels
This change enables the DMA CMD scheduling as default for
video mode panels.

In video mode panel, if the DMA is triggered very close to
the beginning of the active window and the DMA transfer
happens in the last line of VBP, then the HW state will
stay in ‘wait’ and return to ‘idle’ in the first line of VFP.
But somewhere in the middle of the active window, if SW
disables DSI command mode engine while the HW is still
waiting and re-enable after timing engine is OFF. So the
HW never ‘sees’ another vblank line and hence it gets
stuck in the ‘wait’ state.
Scheduling the DMA cmd to the first line in VFP fixes
this issue.

Change-Id: If9e5bd1923c012f10dee50c791a2b2b001d97553
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
2020-12-10 04:19:33 -08:00
qctecmdr
5caf284ecc Merge "disp: msm: dp: handle link maintenance failures" 2020-12-08 04:44:42 -08:00
qctecmdr
a493aaf3a2 Merge "disp: msm: sde: flush all event thread work during CRTC disable" 2020-12-08 04:44:42 -08:00
qctecmdr
874ebfeeae Merge "disp: msm: dp: fix page fault from hdcp buffer access" 2020-12-08 04:44:42 -08:00
qctecmdr
285589db6a Merge "disp: msm: sde: update encoder atomic check during qsync usecase" 2020-12-07 23:37:28 -08:00
qctecmdr
59a266aa8e Merge "disp: msm: dsi: Add support for 5nm C-PHY shadow clock" 2020-12-07 17:09:16 -08:00
qctecmdr
ef242b391f Merge "disp: msm: dsi: trigger broadcast commands using DMA start window" 2020-12-07 17:09:16 -08:00
Sudarsan Ramesh
c6b636fe0b disp: msm: dp: validate edid before dereferencing
Currently, when using custom edid from debugfs, the
extensions data inside the edid block is not validated
before dereferencing the extension block.

The fix adds a edid validation function to validate
any custom edids before accessing any members in the
edid block.

Change-Id: I8a2cc45477416a8f8c4cff882bd53d14012e29f4
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
2020-12-07 10:02:42 -08:00
Yashwanth
d069726235 disp: msm: sde: update encoder atomic check during qsync usecase
During wb/cwb usecases, connectors_changed flag will be
set and needs modeset condition will be set to true. This
change updates qsync concurrency check with modeset to
fail atomic check only if there is seamless poms, dms or
dynamic clock scenario.

Change-Id: I1183f25cd45310fbd1d0b5ce67ee3d5dd3660fe0
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2020-12-07 16:15:23 +05:30
Sankeerth Billakanti
0386ae3a6b disp: msm: dp: handle link maintenance failures
Audio off is done before handling link maintenance
requests from sink or receiver. After handling the
link maintenance, audio is enabled without
verifying the success condition of the link
maintenance. If the link maintenance fails, then the
DP link will not be established and source will
not send video data. So, there is no need to
enable audio.

This change will skip the audio enable portion of
the code whenever the link maintenance fails. The
sink may eventually issue another irq_hpd to retry
the link training.

Change-Id: I1e9aab07d6465ab1b5e6f92717ef7288dc85068f
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
2020-12-07 00:07:54 -08:00
Sankeerth Billakanti
656690c02f disp: msm: dp: fix page fault from hdcp buffer access
There are certain cases where the start_auth and cleanup
are scheduled to be executed consecutively on the
sde_hdcp_2x_main thread. When this scenario occurs, the
functions to facilitate hdcp authentication which are
scheduled to execute after the clean needs to be protected
from dereferencing the freed hdcp message buffers.

This change will add a check to prevent dereferencing the
hdcp message buffer after hdcp cleanup is executed.

Change-Id: I669d25b7a6ce751127b1c21228b751eed8da5b38
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
2020-12-07 00:07:46 -08:00
Satya Rama Aditya Pinapala
fcb453c0b8 disp: msm: dsi: Add support for 5nm C-PHY shadow clock
Add support for 5nm DSI PLL C-PHY shadow clocks, which
will be used during dynamic dsi clock switch.

Change-Id: I55b11f2d0cffd8494d4641e9b2de0b88e7229978
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2020-12-05 08:33:29 -08:00
Satya Rama Aditya Pinapala
ae5b602b4f disp: msm: dsi: trigger broadcast commands using DMA start window
As per the HW requirements it is highly recommended to use DMA start
window to trigger  broadcast commands. If not used then it can
result in a hardware hang with the DSI controllers going out
of sync. This behavior is even more prominent in cases of higher
refresh rates. As part of the change we change the default DMA
scheduling behavior to default to maximum possible DMA window
in case it is not specified in the panel device tree.

Change-Id: Ied4df9063664cedbc18ce009054d4e5ecae30ab2
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2020-12-04 20:01:55 -08:00
qctecmdr
348e9b397c Merge "disp: msm: dp: remove debug log output in isr" 2020-12-03 22:53:43 -08:00
qctecmdr
02e82d15e1 Merge "drm: msm: Reset register when NoiseThresh disabled" 2020-12-03 19:16:31 -08:00
qctecmdr
70df5208b0 Merge "disp: msm: sde: ignore HW recovery disable event" 2020-12-03 11:57:17 -08:00
Steve Cohen
2aaadbc5c7 disp: msm: sde: flush all event thread work during CRTC disable
The API to flush the event thread is only flushing the
frame_event work queued on that thread but during disable
the vblank work must also be flushed. Instead of flushing
only frame_events work, flush all work queued on the event
thread worker. Also rename the API to more accurately describe
what it's doing.

Change-Id: Iaf248a2b1bafc9b9a15ae9447b72cdff07509a91
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-12-03 11:26:00 -05:00
Veera Sundaram Sankaran
98c9ba6153 disp: msm: sde: ignore HW recovery disable event
The current SDE driver logic during MDP hang cases is to send a capture
event to user-mode if recovery custom event is registered. Otherwise, it
will enforce a device panic for debugging purpose. This might have a race
condition during the display tear-down sequence as user-mode unregisters
the recovery event when the last frame is in progress. If the last frame
causes any MDP hang, it will result in a device reset. Support only the
event registration to avoid this case, since HW recovery is not expected
to be changed dynamically.

Change-Id: I8a11e1060b239ac6827f1d078e3e396cff4c1325
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-12-02 15:29:19 -08:00
qctecmdr
ee8ad711e9 Merge "disp: msm: sde: use prepare_commit connector callback for DSI" 2020-12-02 15:02:46 -08:00
Tatenda Chipeperekwa
c90f535a24 disp: msm: dp: remove debug log output in isr
Remove all debug logs and replace them with event logs in the isr
path. This change will reduce the likelihood of an interrupt storm
causing a watchdog bark if display threads are being prevented
from completing execution due to debug logs holding the console
lock.

CRs-Fixed: 2810115
Change-Id: I906f19fb73a7501114fd0a62e9ae66c83dde4d5d
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
2020-12-02 12:36:04 -08:00
qctecmdr
13c448e20f Merge "disp: msm: dp: add support for continuous PPS command" 2020-12-02 06:10:50 -08:00
Yuchao Ma
c1263308c7 drm: msm: Reset register when NoiseThresh disabled
The change reset register of noise thresh when disabled.

Change-Id: I2bb13167b52c6ba92e32c4fa9b4f0a57122164ab
Signed-off-by: Yuchao Ma <yuchaom@codeaurora.org>
2020-12-01 23:08:15 -08:00
qctecmdr
d9208128c7 Merge "disp: msm: sde: fix dsc 1_2 rate control parameter" 2020-12-01 21:38:54 -08:00
qctecmdr
7c8f6d1332 Merge "disp: msm: dp: fix DSC and PPS version mismatch" 2020-12-01 21:38:54 -08:00
qctecmdr
7d396c0c19 Merge "disp: msm: sde: always enable prog fetch and fix prefill calculations" 2020-12-01 09:15:53 -08:00
Steve Cohen
4eff2d1bce disp: msm: sde: use prepare_commit connector callback for DSI
Some DSI panels require qsync on/off DCS commands to be sent in
prepare commit phase. Add the hook for sending these commands
to the panel. If these commands are not present in the panel's
device tree node, it will be treated as a NO-OP.

Change-Id: Ida65512fe0214779dfa848f6c7b33644d3934afd
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-11-30 14:02:50 -05:00
Krishna Manikandan
6bf86dc2e5 disp: msm: sde: retain ubwc settings during LA to LE transition
Setting hbb value based on the ddr type of the target is
not supported in trusted vm environment. Add changes to
retain the ubwc configuration programmed by LA during the
transition to LE environment.

Change-Id: I1fa308ea99f815cfe4d1c75a22dbb6f89a806007
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
2020-11-29 20:24:29 -08:00
Jayaprakash
ea5b9b3157 disp: msm: sde: always enable prog fetch and fix prefill calculations
Enabling and disabling programmable fetch dynamically
across different fps can cause dsi underflow/overflow followed
by underrun. Add changes to always enable prog fetch to handle
such cases. Fix needed_prefill_lines calculation for vfp method
of dfps since linetime is constant in this method and hence
prefill lines need to be based on max_fps. For panels whose
linetime varies with fps, the needed_prefill_lines calculation
remains unchanged.

Change-Id: Ib7b68b577ff903fc2359a8e8c4573d62d55c3828
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2020-11-26 14:43:43 +05:30
Amine Najahi
7a9e08de70 disp: msm: dp: fix DSC and PPS version mismatch
Currently, driver hardcodes the DSC version to use
to v1.1 in DP driver even if the sink reports v1.2 in
the DPCD DSC_ALGORITHM_REVISISON register. This causes
a mismatch between the source DSC hardware programming
and the PPS packet information sent to sink.

This change sets the PPS DSC version field to the one
reported by the sink and falls back to v1.1 in case of
DPCD parsing error.

Change-Id: I76fb55b7bf9b3925ae3f408008f3257fc85cef2c
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2020-11-25 13:16:37 -08:00
Abhinav Kumar
6db41ed532 disp: msm: dp: add support for continuous PPS command
Add support to send PPS command with every frame for DP.
This is needed to satisfy the requirement of certain bridge
chips which need the PPS to be sent every frame.

Change-Id: I8711dff41e60d8b1e1c515a5d34a370a2409ce14
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
2020-11-24 18:16:28 -05:00