Add trace points to track credit and debits to the KGSL memory pools.
Change-Id: Ic0dedbade3ecac12e625a08a9be372bd857f68d2
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Neeraja P <neerp@codeaurora.org>
Add bindings for cmn blk pll which will be used by
clients for controlling the cmn blk.
Change-Id: I2f2c20e1438b51d33300c5d567e7e1f3f23e1f72
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
The current PLL set rate does not support determining
the L val at runtime. This updates the determine rate
by doing round off for this requirement. Add support
for the list_register to clk_pll_ops.
Change-Id: Ica85e1408fd7d1b2154b01150728419dbb81de90
Signed-off-by: Chetan C R <cchinnad@codeaurora.org>
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
Update the pre div for ope_clk_src and add the 19.2Mhz support for
sdcc1_apps_clk_src for MONACO.
Change-Id: I7b12b03c6462c2a28ca626d93c06f3bf073c09a0
Signed-off-by: Saurabh Sahu <sausah@codeaurora.org>
Enable Novatek nt36xxx touch driver as a module for Holi GKI.
Change-Id: I03fa37272dcfdd0a5cd845543ef05c768b69587d
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
Enable ADC5 Gen3 driver for Monaco to use ADC on PMIC PM5100.
Change-Id: Iee302236d149941caeee73a0e8d899f692a4a096
Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
Add scaling functions for batt_therm, batt_id and usb_in_i ADC channels
for PM5100. Also add usb_sns_v_div_16 and vin_div_16 channels to list of
supported channels and correct default prescaling value for vbat_sns
channel and full scale ADC current.
Change-Id: I86b86c319bff6df583efab8cc4c877218a79fe56
Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
Add scaling function for batt_therm, batt_id and usb_in_i
and update channel macros for PM5100.
Change-Id: I45d6e8b5788276dd939b60034ae7804ca8d1b73a
Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
Fix different compilation issues found in QBG driver.
Change-Id: I8ac84e8bffb0c875dac34ea5aa82988b3a05e24f
Signed-off-by: Shyam Kumar Thella <sthella@codeaurora.org>
Use debug level instead of error level for certain print in
cnss_pci_enumerate().
Change-Id: I7453c7834ae34aebb902c5050e3c7c5515500d67
Signed-off-by: Yue Ma <yuem@codeaurora.org>
Add mproc related defconfig for direwolf which inlcudes qrtr,
hwspinlock,glink,smem,smp2p,ipc irq bridge and ipc logging
related configurations.
Change-Id: I56287609ca361f363d5dd9a1d2fc16b03d606c3c
Signed-off-by: Arun Prakash <app@codeaurora.org>
Fix compilation issue while Casting a large number type to a smaller type
which may lead to data lost.
Replace ‘null’ with ‘0’ as null is 64bit wide.
Change-Id: Ic77dfac7c920cf3dbdfe459ec435680cb69be2f5
Signed-off-by: Vinay Sudra <vsudra@codeaurora.org>
Few UFS devices are taking a long time to finish its internal
initialization. UFS driver polls fDeviceInit flag which indicates
device initialization completion.
Increase this flag poll time to 5sec to cover support for those UFS
devices as well.
Change-Id: I99e1ed54d57c9fd75bbe1b22ea30553b1ce0fb83
Signed-off-by: Hiren Gohel <vhiren@codeaurora.org>
This change protects from unclocked access if framework calls the
prepare_message() from any condition. Though driver expects to return
from transfer_hardware() if PM is not enabled, this will double sure
to ensure clocks are enabled before further transfer.
Do not serve system suspend if driver is runtime active, let runtime
suspend happen first and then serve system suspend.
Change-Id: I78613a6aefa9a28f2793277152494f36b8c933e8
Signed-off-by: Mukesh Kumar Savaliya <msavaliy@codeaurora.org>
This patch contains changes for adding support for new HSP SoC versions.
CRs-Fixed: 2941918
Change-Id: I170bf26458dbeb84182ead97594c3dc605b1a64f
Signed-off-by: Prateek Raj Singh <pratsing@codeaurora.org>
Excluding the camera headers which includes videodev2.h
to avoid compilation error on some platforms.
Change-Id: I9fe2c6b75914bd77ceff39f7714f542f711b4af6
Signed-off-by: Prasad Mullamuri <prasadmu@codeaurora.org>
Added support for new comanche 1.3 soc ID
CRs-Fixed: 2942015
Change-Id: I2f1be9127db74614b9d5c2f797468da85559c60e
Signed-off-by: Prateek Raj Singh <pratsing@codeaurora.org>
According to datasheet, it needs to set WLAN_EN pin
to low first and then trigger high before do pcie
enumeration, as for the current code logical it
always assumes the default state of the WLAN_EN is
low, which seems not be appropriate. In particular,
one of our customer has it's own module to set
the default state of the WLAN_EN pin, so it's
hard to guarantee the default state is right.
So in order to make sure it has correct power
sequence with WLAN chipset, adding such fix.
Change-Id: I14030ade506cf0625839b4d7e6ca6b090faa1014
Signed-off-by: Chaoli Zhou <zchaoli@codeaurora.org>
Driver is currently using internal APIs to support L0s, ASPM L1
and ASPM L1ss. PCIE ASPM control driver is compliant to PCIE
specification. Hence use this driver in powersupersave mode.
Driver reads the capability of link partner to enable/disable
L0s, ASPM L1 and ASPM L1ss. In order to enable/disable link
power states link, capability register of root complex is modified
based on device tree property. Also add t_power_on value and scale
from device tree which is used by ASPM control driver to calculate
the L1.2 threshold value.
Change-Id: Ibb69c68659cd6b03011d507fab4eeed6ee88ddc4
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
