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894,559 commits

Author SHA1 Message Date
Yue Liu
799ee3d368 Merge remote-tracking branch 'remotes/origin/caf/hid-aksys/main' into msm-5.4
* remotes/origin/caf/hid-aksys/main:
  Change the license from GPL v3 to GPL v2
  Change the license from GPLv
  update the pid&vid for hhg gamepad device
  update the vid name
  Initial commit for project's source code
  Update README.md
  Initial commit

Change-Id: I76ab7baece37327176b8c0be88c757c9f5e1cf4d
[yueliu@codeaurora.org: resolved merge conflicts and remove
 config change into gki_defconfig which is not suggested to]
Signed-off-by: Yue Liu <yueliu@codeaurora.org>
2021-03-16 15:33:50 +08:00
qctecmdr
95755ee91b Merge "drivers: pinctrl: sdxlemur: Add ebi2 support to GPIO 89 and 90" 2021-03-09 12:52:04 -08:00
qctecmdr
fb1a93ae61 Merge "defconfig: Re-enable qcom_edac driver as a module" 2021-03-09 12:52:03 -08:00
qctecmdr
c865ae26b3 Merge "usb: dwc3-msm: Do not powerdown SSPHY if auto suspend is disabled" 2021-03-09 12:52:03 -08:00
qctecmdr
42270f30bf Merge "sched: Enable PELT8 by default" 2021-03-09 09:03:53 -08:00
qctecmdr
b655fdb315 Merge "power: reset: Add snapshot of vm power off driver" 2021-03-09 09:03:53 -08:00
qctecmdr
f73698b6bf Merge "defconfig: Enable TLMM pincontrol for Direwolf" 2021-03-09 09:03:53 -08:00
Aniket Randive
bebc6b630d usb: dwc3-msm: Do not powerdown SSPHY if auto suspend is disabled
On certain platforms, due to a HW issue, the SSPHY keeps
transitioning in and out of p3 whenever we perform any HS
transfers. This leads to a storm of PWR_EVNT irgs.
Fix this by disabling SSPHY autosuspend on such platforms.
Autosuspend will be enabled as part of dwc3_msm_prepare_suspend
so that SSPHY gets a chance to go into P3.

Change-Id: I4e674f780a72a8c4abcb3e6c9f083f23b1faa196
Signed-off-by: Aniket Randive <arandive@codeaurora.org>
2021-03-09 05:08:30 -08:00
Ajay Agarwal
805c7cc16e usb: dwc3: Write necessary registers for dual port enablement
In line with the sequence for primary port, update proper fields
of DWC3_GUSB2PHYCFG and DWC3_GUSB3PIPECTL registers for the
second port of the dual port controller. Update other registers
as required.
While at it, also avoid enabling SSPHY autosuspend if
dis_u3_susphy_quirk is set.

Change-Id: Ib79dba4c6d854fa2bf33a1b7cecf06f988250662
Signed-off-by: Ajay Agarwal <ajaya@codeaurora.org>
Signed-off-by: Harsh Agarwal <harshq@codeaurora.org>
2021-03-09 04:14:56 -08:00
Ajay Agarwal
76c3eb34d1 usb: dwc3-msm: Add support for 2nd set of wakeup IRQs
Certain targets may have a dual port capable host controller.
Add support for the PHY IRQs for the second port. Since the SSPHY
autosuspend will be disabled for such controllers, remove the
support of pwr_evnt_irq as a mandatory IRQ and allow SSPHY to go
into P3 as a part of suspend sequence. Handle the logic
gracefully to maintain single port controllers.

Change-Id: I5a53d6e23f64bec7ae940d23923df310309a28da
Signed-off-by: Ajay Agarwal <ajaya@codeaurora.org>
Signed-off-by: Harsh Agarwal <harshq@codeaurora.org>
2021-03-09 04:14:30 -08:00
Ajay Agarwal
3081acb9e8 usb: dwc3: Add support for 4 PHYs for dual port controller
Add 2 new PHY instances (HS and SS) in dwc3 and dwc3-msm
structures. Probe and initialize them when the controller is
dual port capable. This capability is advertised by cores
supporting only host mode using the DT flag 'qcom,dual-port'.

Update PHY1 flags wherever applicable while maintaining single
port controller support.

Avoid workaround of SSPHY powerdown as a part of HS device
connect because of the known HW issue of the other SSPHY going in
and out of P3 when data transfers are being done.

Change-Id: If52fd6383cc2da8b763c774d2ad688448f90aea0
Signed-off-by: Ajay Agarwal <ajaya@codeaurora.org>
Signed-off-by: Harsh Agarwal <harshq@codeaurora.org>
2021-03-09 17:34:58 +05:30
qctecmdr
cc81b9bed6 Merge "net: stmmac: Add support for Micrel PHY interrupt" 2021-03-09 03:08:56 -08:00
qctecmdr
0bf3d44552 Merge "cnss2: Remove deprecated wake_event" 2021-03-09 03:08:56 -08:00
qctecmdr
9079b45e60 Merge "msm: kgsl: configure macrotiling channels for A680" 2021-03-09 03:08:56 -08:00
qctecmdr
53bc990734 Merge "msm: kgsl: increase GPU snapshot size on A680" 2021-03-09 03:08:55 -08:00
qctecmdr
b011d942a3 Merge "defconfig: sdmsteppe: move DEBUG_FS from perf to debug config" 2021-03-09 03:08:55 -08:00
qctecmdr
087892be64 Merge "Merge android11-5.4.61+ (1d9c43f) into msm-5.4" 2021-03-09 03:08:55 -08:00
qctecmdr
6a0a03bd7e Merge "pci_iomap: fix page fault issue on vmalloc with section mapping" 2021-03-09 03:08:55 -08:00
qctecmdr
a1cfa2594c Merge "cnss2: Check for BT Enable GPIO in QCA6390" 2021-03-09 02:40:38 -08:00
Vivek Kumar
2b22991404 defconfig: Enable TLMM pincontrol for Direwolf
Enable TLMM pincontrol as module for Direwolf target.

Change-Id: I5a82c4ea55b8f34b931cb45eab81927924052521
Signed-off-by: Vivek Kumar <vivekuma@codeaurora.org>
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
2021-03-09 14:52:36 +05:30
Shreyas K K
0f8c4da74b drivers: pinctrl: qcom: Add Pinctrl driver for Direwolf
Add initial driver to support pin configuration with
pinctrl framework for Direwolf SoC.

Change-Id: I7fd92e716eec71fc0cbdced54902f2ddfadedcc0
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
2021-03-09 14:52:19 +05:30
Ping Jiang
bacd2262eb power: reset: Add snapshot of vm power off driver
Add snapshot of vm power off driver as of msm-4.14
'commit 77a20e0a50e1
("power: reset: cache flush before VM restart")'.

Change-Id: I380b16f46429711284bb6717847a1eef5d8ee9b1
Signed-off-by: Ping Jiang <scottjiang@codeaurora.org>
2021-03-09 15:45:57 +08:00
Vinay Sudra
daa90e8b8c defconfig: sdmsteppe: move DEBUG_FS from perf to debug config
Move CONFIG_DEBUG_FS from qgki config to debug config to
avoid android compilation issues.

Change-Id: Idf2f3ea4d3c0fbd837bad9de9de53f42e690d58b
Signed-off-by: Vinay Sudra <vsudra@codeaurora.org>
2021-03-09 10:33:15 +05:30
Qingqing Zhou
399e44118e pci_iomap: fix page fault issue on vmalloc with section mapping
In this case, CONFIG_SMP and CONFIG_LPAE are both not enabled,
CONFIG_ENABLE_VMALLOC_SAVING is enabled. The paddr|size|addr
satisfies PMD_SIZE alignment, will create section mapping not
page mapping, non-LPAE arm32 uses 2-level page table, including
pgd and pte, before remapping it will do unmapping which clears
init_mm->pgd of corresponding addr and memcpy into [VMALLOC_START,
VMALLOC_END) part of current->active_mm->pgd, but this memcpy misses
to sync other vmalloc areas outside [VMALLC_START, VMALLOC_END) with
vmalloc saving feature, the pgd part of addr in other vmalloc
areas is not synced and still holds the stale mappings, if request
addrs fall into other vmalloc areas, then page fault happens for them.

So need to consider other vmalloc areas outside [VMALLOC_START,
VMALLOC_END) with vmalloc saving feature, change into [PAGE_OFFSET,
VMALLOC_END) to include all vmalloc areas, then all pgds of vmalloc
addrs in current->active_mm->pgd will be synced on unmapping, the
pgds of request addrs are cleared, then do_traslation_fault will
be called for zero pgd value, it calls copy_pmd to sync the pgds
from init_mm->pgd to current->active_mm->pgd for request addrs on
remapping.

Change-Id: Ia283d409a20c8fc9951434078332a3badf0f9ed0
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2021-03-08 18:15:04 -08:00
Melody Olvera
3981ad625f drivers: pinctrl: sdxlemur: Add ebi2 support to GPIO 89 and 90
Add ebi2 support to GPIO 89 and 90 and add an ebi2_a function.

Change-Id: I1854aea3011b1d1cf67ebfebddb1c6b60a34a1b1
Signed-off-by: Melody Olvera <molvera@codeaurora.org>
2021-03-08 14:49:27 -08:00
Mohammed Siddiq
712e346e96 cnss2: Check for BT Enable GPIO in QCA6390
QCA6390 requires synchronization between BT and WLAN enable gpio
to avoid power up issue. Add support for QCA6390 in gpio sync
code.

Change-Id: Id2183ff324c9c3059ea81e9137fa49c803feb183
Signed-off-by: Mohammed Siddiq <msiddiq@codeaurora.org>
2021-03-08 12:35:45 -08:00
Shreyas K K
7ceab32885 defconfig: sdmsteppeauto: Enable SCHED_WALT
Enable SCHED_WALT to add support for scheduler
features like WALT, core_ctl, etc.

Change-Id: I7a3c4494b5c2e6545821491e1aee8bf6c4ac3345
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
2021-03-09 00:29:02 +05:30
Shreyas K K
26a1ed16aa defconfig: gen3auto: Enable SCHED_WALT
Enable SCHED_WALT to add support for scheduler
features like WALT, core_ctl, HMP, etc.

Change-Id: I0b4efd6e2127771be65c754fa35770ba359576bd
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
2021-03-09 00:26:43 +05:30
Raghavendra Rao Ananta
35fa09740a defconfig: Re-enable qcom_edac driver as a module
Build the qcom_edac driver as a module. This is to load the driver
as a first stage module, which is needed in order to bypass a build
system limitation.

Change-Id: I14abd0dac5c018ef6d9366711b80c34e1af12bf4
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
2021-03-08 09:34:27 -08:00
qctecmdr
be60e6e783 Merge "defconfig: autogvm: Enable CONFIG_VIRTIO_EAVB" 2021-03-08 06:54:54 -08:00
Suraj Jaiswal
0f3e11d43b net: stmmac: Add support for Micrel PHY interrupt
Add support for Micrel PHY interrupt.
This is required to support Micrel PHY on stmmac driver.

Change-Id: Ic49924199a0e1d2dd95ae3335c079e3d230bc201
Acked-by: Nagarjuna Chaganti <nchagant@qti.qualcomm.com>
Signed-off-by: Suraj Jaiswal <jsuraj@codeaurora.org>
2021-03-08 06:52:17 -08:00
qctecmdr
4783892a2e Merge "defconfig: gen3auto: Add flag to see logging of interrupts" 2021-03-08 03:05:25 -08:00
qctecmdr
d4186e56fa Merge "power: supply: smb1398-charger: disable WIN_OV deglitch for SMB1394" 2021-03-08 03:05:25 -08:00
qctecmdr
dd0bfda085 Merge "defconfig: autogvm: move DEBUG_FS from perf to debug config" 2021-03-08 03:05:24 -08:00
qctecmdr
b23c0ca463 Merge "net: stmmac: Add support for smmu enablement" 2021-03-08 03:05:24 -08:00
qctecmdr
c30b722b43 Merge "msm: kgsl: Add Common Boot KPI marker" 2021-03-08 03:05:24 -08:00
qctecmdr
6b53b0396b Merge "defconfig: gen3auto: move DEBUG_FS from perf to debug config" 2021-03-08 03:05:23 -08:00
qctecmdr
983d9309f2 Merge "scm: enable audio memory api" 2021-03-08 03:05:23 -08:00
qctecmdr
50a886590b Merge "defconfig: autogvm: Enable ARM based SHA1" 2021-03-08 03:05:23 -08:00
qctecmdr
1fbbbe4089 Merge "mhi: dev: netdev: Update logic for valid access of dentry variable" 2021-03-08 03:05:22 -08:00
qctecmdr
c52023969b Merge "char: virtio_fastrpc: Add snapshot of virtio fastrpc driver" 2021-03-08 03:05:22 -08:00
Hui Li
4d372ce01b msm: kgsl: increase GPU snapshot size on A680
Increase GPU snapshot size to 2MB, this will allow a
complete snapshot without omitting some of data.

Change-Id: I2a44c41e867069762340dfde24cc6be527034bb0
Signed-off-by: Hui Li <hul@codeaurora.org>
2021-03-08 18:49:59 +08:00
Hui Li
7523b0c37e msm: kgsl: configure macrotiling channels for A680
For macrotiling change on a680, will affect RB, SP and TP
0 means UBWC 3.0, 1 means UBWC 3.1, this change configures
the RBBM hardware accordingly.

Change-Id: Ife8325a88e37b5b81ef6060c11edb7b7b2aab165
Signed-off-by: Hui Li <hul@codeaurora.org>
2021-03-08 16:12:18 +08:00
Anuj Garg
b79b527a45 char: virtio_fastrpc: Add snapshot of virtio fastrpc driver
This snapshot is taken as of dev-sa8155 branch
commit 18dcf6bbb4a9 ("char: virtio_fastrpc: add dma handle support").

Change-Id: I3a918907a319ee397f99162e57644d07504a5dd6
Signed-off-by: Anuj Garg <anujgarg@codeaurora.org>
2021-03-08 13:12:46 +05:30
qctecmdr
32eb6f2bc1 Merge "soc: qcom: hgsl: decouple ifence and doorbell" 2021-03-07 23:15:51 -08:00
qctecmdr
5d1b67af09 Merge "usb: f_qdss: Avoid wait_for_completion if qdss_disable is called" 2021-03-07 23:15:51 -08:00
Nitesh Gupta
562e6c175b mhi: dev: netdev: Update logic for valid access of dentry variable
Variable "dentry" is valid only if "CONFIG_DEBUG_FS" is set.
Update logic such that "dentry" variable is accessed during
debugfs removal only in valid condition.

Change-Id: I2a1e3e7f312cf316c94e930e15e9528fbeedb9a1
Signed-off-by: Nitesh Gupta <nitegupt@codeaurora.org>
2021-03-08 12:41:50 +05:30
Vinay Sudra
b301d60880 defconfig: gen3auto: move DEBUG_FS from perf to debug config
Move CONFIG_DEBUG_FS from qgki config to debug config to
avoid android compilation issues.

Change-Id: I0ea781d92f7db79cd49f5fea884de2b023787b3a
Signed-off-by: Vinay Sudra <vsudra@codeaurora.org>
2021-03-08 12:41:06 +05:30
Vinay Sudra
23d1df3555 defconfig: autogvm: Enable ARM based SHA1
Enable ARM HW SHA1 Digest algorithm for faster
digest generation.

Change-Id: I6cad0d189c5c60fb8cffd16fc0e1b82903088350
Signed-off-by: Vinay Sudra <vsudra@codeaurora.org>
2021-03-08 12:38:19 +05:30
Pavankumar Kondeti
b54bff628b sched: Enable PELT8 by default
Lets improve performance on builds which don't have WALT enabled.

Change-Id: I0ed4c99a6a36d0c0efcfc211ebf817b281502196
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
2021-03-08 11:43:06 +05:30