Changes are made to add wrapper function to add a minidump
partition. Also, to add evt log to minidump.
Change-Id: I1204a965bab9db72cb3d381a2817dbe8ef723c66
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
The usb controller driver does not know if DP is
supported / connected and whether it is operating in
concurrent mode. So, whenever there is a ucsi role switch
call to the usb controller driver, it will reset the usb
phy irrespective of DP connection.
The phy reset while DP driver is still processing cable
connect or disconnect will cause aux timeout or NOC errors.
This change will inform the usb controller driver about the
multi_func mode support to convey how many lanes DP will
be using.
Change-Id: I9e96ed399e879820ddd238cf0fbed7069f1de60d
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
get unifdef explicitly when enabled with argument
Change-Id: I9f12da913c7058279f14ecceedde3bfe64be9086
Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>
Signed-off-by: Abhijith Desai <abdesai@codeaurora.org>
During wait for commit done failure cases in the current
code in video mode and command mode(posted start), global
atomic state for current crtc state will be assigned NULL
during state swap which will lead to crash while using
drm_atomic_crtc_state_for_each_plane API. Also in such
timeout cases, border color staging and kickoff being
done without any vblank wait might lead to inconsistent
state because of configuration overriding from the next
commit. Since the timeout is observed at the end of commit
cycle, only soft reset should be done here and remaining
in the next commit cycle.
Change-Id: I0d42dc27035f4f79394aeec347d797c99ed76e5f
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Previous logic expected rsvp_nxt to always be the 2nd rsvp for
a given encoder. This does not work for releasing back-to-back
test-only reservations (with no current rsvp). If new
resources become available between the 2 test-only commits we
may end up reserving more resources than necessary. Change the
logic by adding a pending flag to the rsvp to simplify lookup
of both current and pending/next resource reservations.
Change-Id: Iefa8085f1b4c0cf49bb744dcc2deb7fb92608454
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
In some cases while transitioning between vm, vblank
work might be get executed on event thread after handoff is
completed on commit thread leading to crash. This change
flush the event thread queue during vm pre-release before
lending the io resources to the other vm.
Change-Id: I6a504fc2cec1c4985f7674bbca7fc5869bd8ad07
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Chroma sample types H1V2 and H2V1 are not supported in write back output.
Made changes to add atomic check for such unsupported output formats in
writeback.
Change-Id: Ic37865e0b0c64016df728cc753ad66c3b9e9d138
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
Add support to use atomic variable instead of spinlock
for register logs during register write. This change
helps in reducing the run-time and is safe to use as
most of the register writes happen in commit context.
Change-Id: Ib7e377f80cbf437e391792b0b424cbd1eefdf497
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Currently, 4K120 mode is being filtered by DP driver
due to invalid topology assignation. When 4 LMs are
needed, the number of DSCs must match the number of
LMs since only DSCMERGE based topologies are supported
for driving DSC capable panels.
This change fixes the topology validation logic and
aggregates LM and DSC validation functions in the topology
one since the number of LMs and DSCs must now be considered
in calculating the topology requirement.
Change-Id: I95577eabb34068cd490d23e70ffbb899d1c2d03a
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
This change exposes capabilities for CWB ROI to userspace
as well as implements the cropping feature which is now supported.
Change-Id: Idf76727175bf7c183367be715eaa45f3a432640c
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
1. When panel esd check fails, rc_state request to ON will occur
in event thread.
2. This ON state is not guaranteed since idle pc event can occur
in parallel on commit thread if frame pending count reaches 0.
3. ESD thread is trying to switch vsync at this point to avoid RSC
hang, but idle pc event has disabled clocks causing NOC error.
To avoid such condition this patch re-schedules idle work which
allows completion of display failure notification before the device
enters idle state. This re-scheduling is achieved by modifying early
return in rc_restart_delayed introduced as part of commit 63107e09b3
("disp: msm: sde: allow delayed_off_work scheduling always").
Change-Id: Ie1a1964b92fe1c681cdf0fc5e10591ef14b2d4c3
Signed-off-by: Mahadevan <mahap@codeaurora.org>
Fix copyright with appropriate year in hw dsc file.
Change-Id: I77031951e980e622630869c9df2cf9c673da1454
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
When LTM is switching on/off, merge_mode bit value gets toggled between
0x1 (dual pipe merge configuration) and 0x0 (single pipe configuration).
It is illegal to reconfigure LTM to/from dual-pipe merge mode before
both LTM instances have completed their current workloads. This change
adds support to disable merge_mode one frame after histogram is disabled
to make sure both hardware instances are completely idle and avoid
corrupted histogram data collection.
Change-Id: I9a6b5cbfb69e8af7936749e57fe7c8f7c2703b95
Signed-off-by: Ping Li <pingli@codeaurora.org>
When SW writes to the CTL_SW_RESET register, the hardware
enters a sequence to stop pending OTs and once that’s done
it asserts sw_reset to that CTL path for exactly 100 mdp_clks.
This is hardcoded in the HW design for many generations. The
sw_reset propagates to all the MDP hardware blocks on mdp_clk
and pixel_clk. When the mdpclk : pclk ratio is greater than 100
mdp_clk pulse isn’t long enough to reset the read side. So,
the async FIFO (i.e. the hardware responsible to transfer pixels
from mdp_clk to pixel_clk) only gets partially reset. The mdp_clk
side is reset but the pixel_clk side does NOT. The async FIFO is
in a bad state and believes there’s data in the FIFO. At this
point, the "valid" sent to DSI controller gets flatlined high
and DSI believes transfers are initiated eventually leading
to underflow once panel commands are initiated.
Add changes in software sequence to avoid triggering ctl_reset
to due to above HW limitation.
Change-Id: Iae44dba6ef59cbd5869a7f336af5dd38f93eafdd
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Below is the sequence during which issue is observed
while using stale lut values:
1) Scaler block is enabled in the VIG pipe along with the
valid lut configuration.
2) Idle work gets scheduled and GDSC is turned off erasing
the saved lut values.
3) At the same time, userspace sends a commit assuming lut
values are still valid resulting in artifacts on the
screen.
In the plane state scaler config, only lut flag will be
reset for subsequent commits and remaining properties such
as filter cfgs, lut_idx etc. remains same. This change
caches the lut flag in sde plane whenever the lut is being
set and reuses this flag to handle above issue.
Change-Id: Ice22f811ecc8094834f66e2020d33b01bb951bb0
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
During one of the DP timeout usecases, flush doesn't take
effect due to vid vblank wait failure. As a result, smmu
faults are observed because of fetching the previously
staged planes. This change adds ctl reset in the same
DP atomic commit context to recover and avoid
smmu faults.
Change-Id: I2f9aceca56e27f140607317f7596d6fe0d908af8
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
In DLKM builds, all the display symbols are included as part
of msm_drm.ko and symbols are dynamically linked while
loading ramdumps. This change removes static specifier for
sde_dbg_base in order to access the variable from ramparser
and extract the required logs with the help of ramparser
tool and also in automation stability runs.
Change-Id: I3eae0bc9db3bd285642bf9f7930a31ab47c446e3
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
In CPHY, packet header and checksum is sent twice and SYNC is
sent in between two headers. So, increase packet overhead used
in clock calculation to 15 bytes. Packet Header: 8 bytes,
CRC: 4 bytes, SYNC: 2 bytes and dcs command: 1 byte.
Change-Id: I7a1160cbb57ba4f1faeb4b36a16c322e6069d58f
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Add changes to fix the null dereference in
drm_atomic_get_property caused by connector->state
being NULL. This change allows the drm_mode_config_reset
operation to happen before drm_dev_register to avoid this.
In current scenario, connector->state->crtc is being
accessed due to call to drm_mode_getconnector ioctl with
the drm_mode_config_reset operation pending.
Change-Id: I374d9485819fad85100d1837f4ae22fc2a3ccc40
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
As per the HW teams guidelines, allow dumping the status of
all the HW blocks blocks at every test point.
This code brings in the following changes
1) Featurize the hw block and test point range per target.
2) Reduce the debug bus entries and decrease the static
memory foot print.
3) Allow analyzers to be integrated into the new format.
Change-Id: Ic3bc2c1b77f5617b0f81a2066b22e50cfd6ff8dd
Signed-off-by: Mahadevan <mahap@codeaurora.org>
Add changes to configure register writes in the event
log dump. The register writes can be enabled in the dump
through the debug_fs command.
Change-Id: I08154e193f670999746fbb30291a866db85c8c8d
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
With WB encoder added in the drm encoder_list before primary
encoder introduced as part of commit d28ebf05f4 ("disp:
msm: sde: populate WB display encoder list before dsi"),
sde_kms_wait_for_commit_done during CWB usecase is causing
crtc_commit thread to wait for two WB frame done irqs causing
janks on primary. Add changes to unblock crtc_commit thread and wait
for only one WB frame done irq.
Change-Id: Ie298302fea9df8ba5a1c2fa04f5f585ae455e0c9
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
This change adds pending ctl recovery mask in sde kms
structure to check if there are any ctl paths pending
for recovery and stages only border fill during such
conditions to avoid device crash. Below is the issue
sequence observed during the crash:
1) On one of the ctl path, flush didn't take effect and
flush bits are still pending.
2) It was a NULL flush and last good flush on that
interface has DMA2 pipe staged along with other pipes.
3) Different ctl path re-uses the DMA2 pipe (attached to
ctl path in #1) causing wr_ptr timeout followed by
ppdone timeout.
Change-Id: I07eb9f2fe41f59963dc27655c551c05abe240392
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Newer Android builds to not have headers_install as an executable
Change-Id: Iab81cd0ed9791e7426719fbc1b43d9ccafc89bb7
Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>
