Commit graph

1,874 commits

Author SHA1 Message Date
Andhavarapu Karthik
82f6c103e8 disp: msm: sde: copyright fix for hw dsc file
Fix copyright with appropriate year in hw dsc file.

Change-Id: I77031951e980e622630869c9df2cf9c673da1454
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
2021-03-16 19:22:44 +05:30
Ritesh Kumar
72f31fb34b disp: msm: dsi: update CPHY command mode clock calculation
In CPHY, packet header and checksum is sent twice and SYNC is
sent in between two headers. So, increase packet overhead used
in clock calculation to 15 bytes. Packet Header: 8 bytes,
CRC: 4 bytes, SYNC: 2 bytes and dcs command: 1 byte.

Change-Id: I7a1160cbb57ba4f1faeb4b36a16c322e6069d58f
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
2021-03-04 00:08:32 +05:30
qctecmdr
9025759e47 Merge "disp: msm: sde: fix null dereference in drm_atomic_get_property" 2021-02-25 02:45:53 -08:00
Jayaprakash
ddbcaa93eb disp: msm: sde: fix null dereference in drm_atomic_get_property
Add changes to fix the null dereference in
drm_atomic_get_property caused by connector->state
being NULL. This change allows the drm_mode_config_reset
operation to happen before drm_dev_register to avoid this.
In current scenario, connector->state->crtc is being
accessed due to call to drm_mode_getconnector ioctl with
the drm_mode_config_reset operation pending.

Change-Id: I374d9485819fad85100d1837f4ae22fc2a3ccc40
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2021-02-23 12:04:23 +05:30
qctecmdr
a8f586de25 Merge "disp: msm: re-factor debug bus logic to dump all test points" 2021-02-22 10:33:58 -08:00
qctecmdr
8912e4e675 Merge "disp: msm: sde: add optional sde register writes in event logs" 2021-02-22 07:43:48 -08:00
qctecmdr
f52f288196 Merge "disp: msm: sde: add changes to wait for only one WB_DONE irq" 2021-02-22 07:43:48 -08:00
Mahadevan
081fc6a13b disp: msm: re-factor debug bus logic to dump all test points
As per the HW teams guidelines, allow dumping the status of
all the HW blocks blocks at every test point.
This code brings in the following changes
1) Featurize the hw block  and test point range per target.
2) Reduce the debug bus entries and decrease the static
   memory foot print.
3) Allow analyzers to be integrated into the new format.

Change-Id: Ic3bc2c1b77f5617b0f81a2066b22e50cfd6ff8dd
Signed-off-by: Mahadevan <mahap@codeaurora.org>
2021-02-18 11:35:00 +05:30
Chandan Uddaraju
5d955fca0e disp: msm: make msm_drm as module for normal builds
Make msm_drm as DLKM(Dynamically loadable kernel
module) for default configuration.

Change-Id: Ifd84d8c5e1f27384b0db4a89806788ce9a3d7a3c
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
2021-02-17 13:24:13 -08:00
Jayaprakash
bd3e9f6c14 disp: msm: sde: add optional sde register writes in event logs
Add changes to configure register writes in the event
log dump. The register writes can be enabled in the dump
through the debug_fs command.

Change-Id: I08154e193f670999746fbb30291a866db85c8c8d
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2021-02-17 05:27:25 -08:00
Jayaprakash
32a5a1fa8c disp: msm: sde: add changes to wait for only one WB_DONE irq
With WB encoder added in the drm encoder_list before primary
encoder introduced as part of commit d28ebf05f4 ("disp:
msm: sde: populate WB display encoder list before dsi"),
sde_kms_wait_for_commit_done during CWB usecase is causing
crtc_commit thread to wait for two WB frame done irqs causing
janks on primary. Add changes to unblock crtc_commit thread and wait
for only one WB frame done irq.

Change-Id: Ie298302fea9df8ba5a1c2fa04f5f585ae455e0c9
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2021-02-17 13:04:14 +05:30
qctecmdr
0513e3ef42 Merge "disp: msm: sde: add pending ctl recovery mask in sde_kms" 2021-02-16 22:24:13 -08:00
qctecmdr
f4e8bb8e3a Merge "disp: msm: dsi: change rule to initialize display in firmware" 2021-02-14 07:49:13 -08:00
Yashwanth
254ccadf2d disp: msm: sde: add pending ctl recovery mask in sde_kms
This change adds pending ctl recovery mask in sde kms
structure to check if there are any ctl paths pending
for recovery and stages only border fill during such
conditions to avoid device crash. Below is the issue
sequence observed during the crash:

1) On one of the ctl path, flush didn't take effect and
flush bits are still pending.

2) It was a NULL flush and last good flush on that
interface has DMA2 pipe staged along with other pipes.

3) Different ctl path re-uses the DMA2 pipe (attached to
ctl path in #1) causing wr_ptr timeout followed by
ppdone timeout.

Change-Id: I07eb9f2fe41f59963dc27655c551c05abe240392
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-02-12 19:39:50 +05:30
qctecmdr
edd498ab69 Merge "display: Use sh to execute install script" 2021-02-11 08:00:26 -08:00
qctecmdr
d6e821b36c Merge "disp: msm: dsi: Update ctrl & phy refcounts for defer probe" 2021-02-11 03:33:33 -08:00
qctecmdr
243880b462 Merge "disp: msm: sde: add on/off and payload size logging for LUTDMA" 2021-02-08 21:46:24 -08:00
Naseer Ahmed
228cba9357 display: Use sh to execute install script
Newer Android builds to not have headers_install as an executable

Change-Id: Iab81cd0ed9791e7426719fbc1b43d9ccafc89bb7
Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>
2021-02-08 15:50:05 -05:00
qctecmdr
a5857a5b3a Merge "disp: msm: sde: allow delayed_off_work scheduling always" 2021-02-05 06:06:26 -08:00
qctecmdr
4afe1c3231 Merge "disp: msm: sde: add kickoff_in_progress flag in sde crtc" 2021-02-04 23:26:21 -08:00
Jayaprakash
63107e09b3 disp: msm: sde: allow delayed_off_work scheduling always
Add changes to allow delayed_off_work scheduling in all cases.
Skip scheduling only in panel_dead cases where delay_kickoff
is enabled. This will fix the issue seen with commit 08d04c2f3b
("disp: msm: sde: avoid rc restart when triggered from panel dead").

Change-Id: I4c9a7cd26af9d99ecd3f58023a6fb6d041d91e92
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2021-02-05 12:32:56 +05:30
Rajeev Nandan
748047743e disp: msm: dsi: change rule to initialize display in firmware
Request for display in firmware only if no display enabled form
the UEFI.

In the targets supporting dual DSI display having both displays
DT nodes part of the connector list, if only one display is
enabled from the UEFI, then the driver requests for display
in firmware for the second display. Getting the display panel node
from firmware is time taking process, and it can take up to
ten seconds. This causes a delay in adding the component for the second
display, resulting in a delay in bind calls for components of the
msm drm driver.

Change-Id: Ic0aa5ca890fc874d38d3e7eef745f2942e12f9bc
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
2021-02-05 10:56:14 +05:30
qctecmdr
2b0b08b777 Merge "disp: msm: sde: avoid rc restart when triggered from panel dead" 2021-02-03 01:52:17 -08:00
qctecmdr
5f1da40288 Merge "disp: msm: dsi: Fix DFPS sequence when constant fps is enabled" 2021-02-03 01:52:17 -08:00
qctecmdr
6059d12a04 Merge "disp: msm: dp: fix to handle host ready failues" 2021-02-03 01:52:17 -08:00
qctecmdr
53034fd230 Merge "disp: msm: dsi: fix boot display name parsing" 2021-02-03 01:52:17 -08:00
Yashwanth
8d2eb871fb disp: msm: sde: add kickoff_in_progress flag in sde crtc
In dual display usecases, during pm suspend/resume,
commit is scheduled only on primary crtc thread. If idle
timeout value is very short such as in LP2 mode, it might
result in race condition due to idle pc off work getting
scheduled on its crtc thread. This change adds kickoff in
progress flag to handle such cases as crtc frame pending
count is only updated after rc kickoff.

Change-Id: Iebb331d914b23cc5eeadfeb2a488891e88b3202a
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-02-03 09:38:58 +05:30
Ritesh Kumar
49a0dd3ef4 disp: msm: dsi: Fix DFPS sequence when constant fps is enabled
When DFPS and dynamic clock switch with constant fps are
enabled, wait for dynamic refresh done only if clock switch
is triggered. In case where only fps changes, clock remains
same. So, wait for dynamic refresh done is not required.

Change-Id: I1a96d8d6756086afe2cd6e5bdc19be27c2ffed92
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
2021-02-02 02:40:32 -08:00
Lipsa Rout
d2791ff131 disp: msm: dsi: Update ctrl & phy refcounts for defer probe
ctrl and phy refcounts get incremented even on deferring probe
for display panels which need backlight through wled.As a
result, while probing, it considers that the device is already
in use. This change decrements the ctrl and phy refcounts for
defer probe.

Change-Id: Ica1f5712dd28ed4c635946f2ac89d5f4f074a4c5
Signed-off-by: Lipsa Rout <lrout@codeaurora.org>
2021-02-01 10:02:16 +05:30
Rajeev Nandan
08493b414c disp: msm: dsi: fix boot display name parsing
The boot_disp_en flag for secondary display is getting enabled
all the time, even if its boot_param string is empty.
Correct the boot display name parsing from boot_param string
to fix this issue.

Change-Id: Ica1465611f592b22518061987571919838914891
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
2021-01-27 22:57:30 -08:00
Yuan Zhao
0b595d4f3e disp: msm: dsi: defer clk setting when doing const_fps RFI
When doing const fps RFI, dynamic refresh clock was done
in the next frame kick off, so as the orginal RFI work flow,
the clock setting also should be done here.

Change-Id: Ic3e6a35dc7264df028f5d848ac6f1eea04a95126
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
2021-01-27 21:08:32 -08:00
qctecmdr
63e8367aad Merge "disp: msm: sde: program ob_max_addr based on dsc native422 support" 2021-01-24 22:33:27 -08:00
qctecmdr
e050ac9168 Merge "disp: msm: dp: check for pixel1 rcg only for mst supported platforms" 2021-01-24 22:33:27 -08:00
Rajat Gupta
919ff0b397 disp: msm: dp: check for pixel1 rcg only for mst supported platforms
Check for pixel1 rcg only for mst supported platforms. On sst only
devices bind gets failed.

Change-Id: I73cc4a572d4d0791205c342f57618b226eb91fef
Signed-off-by: Rajat Gupta <rajatgu@codeaurora.org>
2021-01-22 19:03:03 +05:30
Andhavarapu Karthik
fb15676492 disp: msm: sde: program ob_max_addr based on dsc native422 support
Current code does output buffer max_addr calculation based on dsc id.
Made changes to calculate ob_max_addr based on dsc native422 support.

Change-Id: I01922750f1e9d6cb45615acc1c473891fc648e5d
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
2021-01-22 15:42:30 +05:30
qctecmdr
277dae9485 Merge "disp: msm: dp: avoid setting multi_func when pin value is zero" 2021-01-21 21:03:30 -08:00
qctecmdr
89a9afa727 Merge "disp: msm: sde: disable uidle for yupik target" 2021-01-20 22:56:44 -08:00
Mahadevan
08d04c2f3b disp: msm: sde: avoid rc restart when triggered from panel dead
This change prevents scheduling of rc_restart in case of
panel dead. This early return is required to avoid the list
add corruption when a race condition happens between event
thread and commit thread. When event thread is handling
display failure notification if the virt_enable arrives in
commit thread it will reinizialize kthread for
delayed_off_work without deactivating the existing list
which leads to linkage corruption.

Change-Id: I41d08cd47ba6f887f0860e52bcddf414085524bb
Signed-off-by: Mahadevan <mahap@codeaurora.org>
2021-01-20 21:02:31 +05:30
Andhavarapu Karthik
c771326b63 disp: msm: sde: disable uidle for yupik target
Made changes to disable uidle feature in yupik target.

Change-Id: If122a86ed14002399e2dbd0b62385d47c854136f
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
2021-01-20 15:56:47 +05:30
Yashwanth
7277a3f2f2 disp: msm: sde: save register write logs in dump
Changes are made to add register write logs to memory dump.
This can be extracted from crash dumps and used for analysis.

Change-Id: If46aaa4ae68f83c79d4b51cbe5dfd22340aa991d
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-01-18 16:50:39 +05:30
Narendra Muppalla
286a52ba84 disp: msm: sde: use different spin lock for frame events
Due to lock sequence inconsistency between sde_crtc->spin_lock and
sde_kms->hw_intr->irq_lock can cause deadlock, to avoid this possible
deadlock this change uses different spin lock for frame events.

Change-Id: I51b1184dfa1069c87653099b95b992b277721daf
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2021-01-16 20:20:58 -08:00
Rajat Gupta
0654925436 disp: msm: dp: fix to handle host ready failues
Handle host_ready failures and try to initialize host if not already.
Sometimes customizations for customers causes NOC error as host_ready
doesn't return early upon failure and the customer customization
tries to access aux register to reconfig upon aux failure while
reading EDID. Adding fix will make driver more robust to handle such
cases.

Change-Id: Ifa5c56daa32c4ef366a0e05718495ffcb40b96b3
Signed-off-by: Rajat Gupta <rajatgu@codeaurora.org>
2021-01-15 15:26:15 +05:30
qctecmdr
87440766f3 Merge "disp: msm: dp: add support for 7nm pll" 2021-01-14 23:05:05 -08:00
qctecmdr
a5441c0cba Merge "disp: msm: sde: fix potential race condition" 2021-01-14 23:05:05 -08:00
Rajkumar Subbiah
fe1caa0eb9 disp: msm: dp: avoid setting multi_func when pin value is zero
During dp altmode driver initialization, the dp altmode driver is called
with a null data packet. Even though this callback indicates a disconnect,
the multi function flag is incorrectly set to true. If the DP is enabled
later using simulation mode, the multi function flag is not cleared thereby
limiting the lane count to 2 irrespective of capability applied through
DPCD.

This change checks for the zero pin value while setting the multi function
flag.

Change-Id: I974fbf1630eed26f406ac9e4c99140b27f0cb635
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
2021-01-14 17:03:31 -05:00
Rajat Gupta
557d8d3fa5 disp: msm: dp: add support for 7nm pll
Add support for 7nm pll. Only some offsets are different from 5nm
pll while the rest are same.

Change-Id: If61cd604d7f8221c659f1b83761647e86e3b6627
Signed-off-by: Rajat Gupta <rajatgu@codeaurora.org>
2021-01-14 02:54:05 +05:30
Andhavarapu Karthik
aa20b1c188 disp: msm: sde: add cwb virtual mixers support
In yupik target, cwb path has pingpong block without any layer mixer.
Add virtual mixer to support reservation of pp block in such case.
This virtual mixer will be used only for cwb use case.

Change-Id: Iacc1a3f5e7d99d9fc36288450b0e19081b3ef763
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
2021-01-13 14:00:22 +05:30
Ping Li
6a80184cdb disp: msm: sde: fix potential race condition
Move the hist irq handling out of callback function, i.e., the hw
interrupt irq_lock context, to avoid dead lock between crtc spin_lock
and irq_lock. This change also extends crtc spin_lock coverage in
_sde_cp_crtc_enable_hist_irq to prevent null pointer dereference on
event node, which can be deleted during crtc event de-registration.

Change-Id: Iadaed54ab93c4c4abe065a8762d2addccb0c65c6
Signed-off-by: Ping Li <pingli@codeaurora.org>
2021-01-12 18:40:18 -08:00
Christopher Braga
6a17186293 disp: msm: sde: add on/off and payload size logging for LUTDMA
Debugging of LUTDMA has proven to be difficult due to lacking
information. Add logging for payload sizing, feature on / off,
and dumping of 64-bit buffer addresses.

Change-Id: I6d421f65172a782b79e915501ec9ea00d05dbcdd
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2021-01-12 12:45:33 -05:00
qctecmdr
5dcc9ed436 Merge "disp: msm: clear dma done interrupt status for slave controller" 2021-01-11 05:47:59 -08:00