Commit graph

893,620 commits

Author SHA1 Message Date
Veera Vegivada
84abd630f7 arm64: defconfig: Enable SM6150 interconnect driver
Enable the SM6150 interconnect driver so that consumers are
able to obtain their path handles properly.

Change-Id: Ie6b99d37f73b69dc375426d64e9148b9a64180f5
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2021-01-25 18:29:48 +05:30
qctecmdr
52da8f55ee Merge "msm: kgsl: Add enable_signaling for timeline fence" 2021-01-24 22:54:19 -08:00
qctecmdr
cbef52ce19 Merge "power: smb358: Add support to make SMB358 driver GKI complaint" 2021-01-24 22:54:19 -08:00
Zhiqiang Tu
f9bd900b8a i2c: virtio: Add snapshot of virtio i2c driver
Add snapshot of virtio i2c driver from msm-4.14.
This snapshot is taken as of msm-4.14 commit 972d72613cd1
("i2c: virtio: Fix return value issue of transfer function").

Change-Id: Idb4f6b5918f7d7237146d02839638b8a97a05c02
Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
2021-01-24 05:11:10 -08:00
qctecmdr
e168b52f6b Merge "msm: pcie: Add tcsr configuration" 2021-01-23 23:36:22 -08:00
qctecmdr
b368317cea Merge "clk: qcom: gpucc-yupik: Remove GPUCC PLL0 configuration from HLOS" 2021-01-23 23:36:22 -08:00
Hardik Kantilal Patel
2273a9e6c9 ICNSS2: Enable Runtime PM feature for Moselle
Enable Runtime PM feature for Moselle.

Change-Id: I210a77052a25067802ca74eb82ad2a045d4c7dbc
Signed-off-by: Hardik Kantilal Patel <hkpatel@codeaurora.org>
2021-01-23 19:08:33 +05:30
qctecmdr
c522f59658 Merge "iommu/arm-smmu: Fix SMR mask extraction for bootloader programmed SMRs" 2021-01-22 21:12:24 -08:00
qctecmdr
22e7b8f5e9 Merge "msm: pcie-ep: Use default PCIe CLKREQ# settings" 2021-01-22 21:12:24 -08:00
qctecmdr
8349627940 Merge "msm: cvp: Support handling cp camera buffer" 2021-01-22 17:31:16 -08:00
qctecmdr
ccffb23bfa Merge "msm: kgsl: Enable Preemption on A635 GPU" 2021-01-22 17:31:16 -08:00
qctecmdr
4d6ec09334 Merge "defconfig: Configure MaxPower to 900mA" 2021-01-22 17:31:15 -08:00
Isaac J. Manjarres
8b27d2333a iommu/arm-smmu: Fix SMR mask extraction for bootloader programmed SMRs
When extracting the mask for an SMR that was programmed by the
bootloader, the SMR.valid field is also extracted and is treated
as part of the mask. This causes issues when removing an SMMU
master, as removing the master involves constructing an SMR
entry with the mask and SID without the valid bit set and writing
that value to the SMR. However, since the valid bit was part of
the mask, the SMR will still be valid.

Instead, remove the valid bit from the raw SMR value that is used
for extracting the SMR mask.

Change-Id: Iccada2c474b196200ae1b56eb9faa9cb026f5ef1
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2021-01-22 15:41:13 -08:00
Siddartha Mohanadoss
7328656346 msm: pcie-ep: Use default PCIe CLKREQ# settings
Use default settings for CLKREQ# from pinctrl DTSI.
Configuring the GPIO in the HLOS driver is causing the
PCIe controller to go down and any DBI access is causing
a NOC error. Since this GPIO is not configured during
resume or sleep the driver can rely on the pinctrl settings
that is programmed as part of the TLMM driver initialization
of the GPIO as default.

Change-Id: Ib6a62e6aa471c39858302fdc0e575fc7ab5abff4
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
2021-01-22 15:33:35 -08:00
qctecmdr
78bb563bf8 Merge "input: qcom-hv-haptics: check playing effect pointer in IRQ handler" 2021-01-22 13:46:45 -08:00
qctecmdr
c1cc7c0229 Merge "usb: core: Reduce resume signalling time for devices behind external hub" 2021-01-22 13:46:44 -08:00
qctecmdr
e9b58393fb Merge "pinctrl: qcom: Expose ufs_reset as gpio on sm6150" 2021-01-22 13:46:44 -08:00
qctecmdr
6bfe888368 Merge "defconfig: Add configs to enable cpufreq/devfreq" 2021-01-22 13:46:44 -08:00
qctecmdr
63121c3d1e Merge "defconfig: gen3auto: Enable QCOM_SCM" 2021-01-22 13:46:44 -08:00
qctecmdr
a8e20ab52c Merge "defconfig: quinvmauto: Enable hab and peripheral drivers" 2021-01-22 13:46:43 -08:00
qctecmdr
0ef96ce882 Merge "mmc: sdhci-msm: Always set max_busy_timeout as zero" 2021-01-22 13:46:43 -08:00
qctecmdr
eb36342966 Merge "netfilter: Add reset_timer logic to timers" 2021-01-22 13:46:43 -08:00
qctecmdr
e1eeda2440 Merge "icc: dt-bindings: add endpoint IDs for interconnects for SM6150" 2021-01-22 13:46:42 -08:00
Jagadeesh Kona
bbeeb65e4e clk: qcom: gpucc-yupik: Remove GPUCC PLL0 configuration from HLOS
Remove GPUCC PLL0 configuration from HLOS as this PLL would be
configured from Graphics FW.

Change-Id: I97e94d71c941c67dad9e0fe3f2a08d4b36f95103
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
2021-01-23 00:18:27 +05:30
qctecmdr
152d15378a Merge "coresight: cti: Solve boot up issue" 2021-01-22 10:04:02 -08:00
qctecmdr
1dd7418832 Merge "msm: kgsl: Fix nr_removed calculation while reducing pools" 2021-01-22 10:04:02 -08:00
qctecmdr
652039e88a Merge "msm: kgsl: Enable GMU BW scaling and update CP ROQ size" 2021-01-22 10:04:01 -08:00
qctecmdr
c23063ec72 Merge "serial:msm_geni_serial: Handling the cts counter in uart driver" 2021-01-22 10:04:01 -08:00
qctecmdr
f18fc34265 Merge "arm: defconfig: enable firmware loader helper" 2021-01-22 10:04:01 -08:00
qctecmdr
372a5f3f6d Merge "arm64: defconfig: Enable PDC device for sdmsteppeauto" 2021-01-22 10:04:00 -08:00
qctecmdr
7e44485813 Merge "drivers: thermal: Use lock before accessing thermal instance list" 2021-01-22 10:04:00 -08:00
Pranav Patel
55d32239a2 msm: kgsl: Add enable_signaling for timeline fence
Implement enable_signaling for timeline fence. Dma fence driver's
APIs such as dma_fence_add_callback() use enable_signaling for
fence status and correct return value. Implementing this fix
scenarios such as dma_fence_add_callback() returning invalid
return value when timeline has been moved ahead.

Change-Id: Iaad8bf2801802216050e70c1b8ee1e0b2ec87a5f
Signed-off-by: Pranav Patel <pranavp@codeaurora.org>
2021-01-22 23:08:15 +05:30
Nitesh Gupta
b2356dc135 msm: pcie: Add tcsr configuration
Add support for reading tcsr configuration from device tree and
configuring tcsr register dynamically.
This change for supporting sa8195p PCIe1. The default PCIe linkage
status of PCIe1 and 2 on sa8195p is:
PCIe1: not enabled
PCIe2: x4 lane
When config the register TCSR_PCIEPHY_LINK_CONFIG to 0(default 1),
the linkage status becomes:
PCIe1: x2 lane
PCIe2: x2 lane
This change add the ability to read tcsr value from device tree.

Change-Id: Iac53f61a147a839772c8411993f3be233b142b56
Signed-off-by: Xiang Li <lixiang@codeaurora.org>
Signed-off-by: Nitesh Gupta <nitegupt@codeaurora.org>
2021-01-22 09:27:15 -08:00
Elson Roy Serrao
d0aefaf022 defconfig: Configure MaxPower to 900mA
Add the config entry to set the MaxPower to 900mA to accommodate
Super Speed and above.

Change-Id: I7e002b4942d1f5548c6d3281ac89e74f633b5723
Signed-off-by: Elson Roy Serrao <eserrao@codeaurora.org>
2021-01-22 07:56:05 -08:00
Elson Roy Serrao
e1258ce10e usb: gadget: Allow up to 900mA current draw for SuperSpeed
Currently 500mA is used as max allowable current to draw over
USB VBUS. However in SuperSpeed a gadget may draw up to 900mA
Update the CONFIG_USB_GADGET_VBUS_DRAW's allowable range to
be up to 900.

Change-Id: I781308065b30b260437f7b3180e276f6a657f504
Signed-off-by: Elson Roy Serrao <eserrao@codeaurora.org>
2021-01-22 07:52:01 -08:00
Pulkit Singh Tak
3dc3967bb4 msm: cvp: Support handling cp camera buffer
Adding support for cp camera buffer mapping and
new hfi for chroma buffer.

Change-Id: Iadce59b596447c0bbdf4985bdb8c9209df517bae
Signed-off-by: Pulkit Singh Tak <ptak@codeaurora.org>
2021-01-22 20:38:29 +05:30
Pankaj Gupta
e994cb44c2 msm: kgsl: Enable Preemption on A635 GPU
Enable Preemption feature on A635 GPU.

Change-Id: Ieea4cde2fd8678fc50d7d67b3233527a78cfae7a
Signed-off-by: Pankaj Gupta <gpankaj@codeaurora.org>
2021-01-22 16:09:05 +05:30
Sauvik Saha
e5705066a9 netfilter: Add reset_timer logic to timers
-This patch reuses the existing reset_timer logic
while running IDLE and HARDIDLE timers.

CRs-Fixed: 2859971
Change-Id: Ibaa86a30ec4c58eb3fbc2f4f48c9c1af6f33f018
Acked-by: Akash Aggarwal <akasagga@qti.qualcomm.com>
Signed-off-by: Manoj Basapathi <manojbm@codeaurora.org>
Signed-off-by: Sauvik Saha <ssaha@codeaurora.org>
2021-01-22 15:00:18 +05:30
Sarthak Garg
0a5ff911f0 mmc: sdhci-msm: Always set max_busy_timeout as zero
Qcom SDHC uses base clock in calculating the data-timeout
value. So SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK quirk is set.

Moreover discard size calculation uses max_busy_timeout in deriving the
value. So, we can ensure a larger discard size by setting this
timeout as zero. If this timeout is zero then it takes max erase
timeout vlaue (which is 60sec) in the discard size calculation.

But when this quirk is set max_busy_timeout variable gets updated
to non zero value leading to smaller discard size.

Define get_max_timeout_count ops in sdhci_msm_ops which always sets
max_busy_timeout to zero.

Change-Id: Iec6013dde6082b2a8fdb449cacf503c290252d0b
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
2021-01-22 14:47:51 +05:30
Shreyas K K
41a4f32e55 defconfig: gen3auto: Enable QCOM_SCM
Enable communication with secure world on gen3auto
targets.

Change-Id: I72a6227d5b2ca4825cb7614055163bffb4245eea
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
2021-01-22 11:39:32 +05:30
Biao Long
2aa2291a2a defconfig: Add configs to enable cpufreq/devfreq
Add configs to enable cpufreq/devfreq.

Change-Id: I4583ee84a46e047308c7bb5a7920c416706688f7
Signed-off-by: Biao Long <blong@codeaurora.org>
2021-01-21 21:18:12 -08:00
Veera Vegivada
9256ad8778 icc: dt-bindings: add endpoint IDs for interconnects for SM6150
Add master and slave ID constants for all Qualcomm Technologies, Inc.
SM6150 interconnect providers which consumers can use to set bandwidth
constraints and find paths in the NoC (Network-On-Chip) topology.

Change-Id: I883cee60db070c45191b1a7ecec07f90a2c49190
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2021-01-22 10:31:36 +05:30
Veera Vegivada
a9cb978bca pinctrl: qcom: Expose ufs_reset as gpio on sm6150
The ufs_reset pin is expected to be wired to the reset pin of the
primary UFS memory but is pretty much just a general purpose output pin.
Reorder the pins and expose it as gpio 204, so that the UFS driver can
toggle it.

Change-Id: Ia891c0d817b1176df840ea3774776e57497a837f
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2021-01-22 10:22:10 +05:30
Maulik Shah
bf22486306 pinctrl: qcom: Add GPIO to PDC wakeirq map for sm6150
Add GPIO to PDC wakeirq map and update the direct connect
list.

Change-Id: I12f368d840d22fc2e45a70a3abfc45a00cb3848b
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
2021-01-22 10:19:16 +05:30
qctecmdr
dabe161962 Merge "msm: kgsl: Take devfreq event lock for ddr qos vote" 2021-01-21 18:57:27 -08:00
qctecmdr
cfb54b7fe5 Merge "mhi: core: Fix format specifier in mhi_alloc_bhie_table" 2021-01-21 18:57:27 -08:00
qctecmdr
669cc6266d Merge "cnss2: Minor enhancements for the driver" 2021-01-21 18:57:27 -08:00
Fenglin Wu
677f534e51 input: qcom-hv-haptics: check playing effect pointer in IRQ handler
When uploading a constant effect after stopping FIFO play, the effect
pointer in haptics_play_info structure will be set to NULL. If there
is any pending fifo-empty IRQ gets served after that, it will trigger
a NULL pointer dereference issue. To avoid this, check the playing
effect pointer before use it in the IRQ handler.

Change-Id: Iacfea5e48d0a9519fa2c930ec821e395c43b6281
Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
2021-01-21 18:49:29 -08:00
Zhiqiang Tu
c75cb7a377 defconfig: quinvmauto: Enable hab and peripheral drivers
Enable hab, i2c, uart, spi, sdhci, usb and pcie drivers.

Change-Id: I9271d038357142e89d0a212ca25ccfa8345b083d
Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
2021-01-22 09:53:55 +08:00
qctecmdr
b7cbe3beb1 Merge "input: qcom-hv-haptics: ensure HBoost is ready before the play" 2021-01-21 15:17:06 -08:00