Removed marking the static process is closed
in ADSP SSR call back. Any way, this is
handled during the PDR callback.
Change-Id: Idcc358a972546f93cb8e7cd5e28d446e7fd632e1
Acked-by: Nishant Chaubey <chaubey@qti.qualcomm.com>
Signed-off-by: Jeya R <jeyr@codeaurora.org>
This change is for general scheduler improvement.
Change-Id: Ia728ecbc780c9d172b49029ef3c87c6b3b490872
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Add support for IDP and ATP hw platforms in socinfo driver.
Change-Id: Icc2a496d06e57c1869a5129b628c2d095db9186b
Signed-off-by: Yogesh Lal <ylal@codeaurora.org>
The Fmax table is updated as per the HW recommendation for csi3phytimer
clock. Also at the same time remove the unwanted clk set rate flag for
display rot clock.
Change-Id: I761f2cb99da27d4d04dbbf95dd546faefdad225a
Signed-off-by: Taniya Das <tdas@codeaurora.org>
update the debug mux for Silver/Gold/L3 CPU clocks.
Change-Id: I124a998fd63e6d0b63289777890c39812d51ea5d
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Add support for PMX65, which has 16 GPIO pins.
Change-Id: Ib01b5af79570fcb75b4b419c7bba118d2522d225
Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org>
The pm8008 regulator is connected over I2C and the I2C device configures
its clocks in runtime_resume and runtime_suspend. These callbacks are
triggered from the pm8008 driver's regmap calls. This means regulator
framework requests for pm8008 call into the clock framework with the
regulator framework locks held. The qcom clock providers also call into
the regulator framework with the clock framework locks held. If thread A
makes a pm8008 request at the same time thread B makes a clock request,
then it can result in deadlocks. Thread A will be stuck waiting on the
clock locks while thread B is stuck waiting on the regulator locks.
To prevent these deadlocks, enable the I2C clocks required for pm8008 by
default during probe and stop registering them with the framework. This
NOPs any client requests, since of_clk_get() returns NULL when passed an
unregistered clock and all other clock APIs return success before
grabbing any locks when passed NULL.
Change-Id: If308d3dab36a1ef9650256a0343789c2aaf56930
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
Drop WFC QMI indications from FW / IMS based on corresponding
connection status withs platform driver.
Change-Id: Ifa5877e551503e371750cbc7fdf958cc975725dd
Signed-off-by: Manikandan Mohan <manikand@codeaurora.org>
Add gpu_cc_cx_gmu, gpu_cc_hub_aon & gpu_cc_hub_cx_int clock to the
list of clocks to vote for in order to access the KGSL SMMU register
space.
Change-Id: I84ff20b1c05c9045c3b271cd85ea98957fc4a6ce
Signed-off-by: Raghu Ananya Arabolu <rarabolu@codeaurora.org>
For a619_holi GPU, use RBBM_GBIF_HALT registers to halt GX
traffic and poll for the ack.
Change-Id: Iaae9084a04a5acc05ae5561d0a3c44da0ab5cebb
Signed-off-by: Pankaj Gupta <gpankaj@codeaurora.org>
In many cases display panel information may not be available when the
touch driver is being probed. This change defers the probe if the
panel is not found to ensure that the correct touch driver is probed.
Change-Id: I52b8cd49342b6213639eefb8f10876178612af49
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
cpuinfo.min_freq/max_freq gives the real min/max frequencies available.
whereas policy min/max offer current min/max of the policy, which
may be the desired values set by any other client like msm_perf or
even a postboot setting. This can potentially limit min/max
frequencies ranges.
Change-Id: Ia7978ccd99b419f68d06fec24dac1adfacff36b7
Signed-off-by: Kishore Sri venkata Ganesh Bolisetty <bsrivenk@codeaurora.org>
For all A615 GPU family GMEM base start with 1MB as
per requirement.
Change-Id: Ie4ca5b9d264492f10eff39daf758d5c72d32c653
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
Currently, access to a secure channel is not allowed using the
non-secure device node. However, since OEMs could configure all
remote subsystems as secure, allow access to a secure channel even
when the application has opened the non-secure node, if the domain
supports unsigned PD offload.
Change-Id: I64ad1f57098cedfe2663c2b975c74bfdc74a3947
Acked-by: Thyagarajan Venkatanarayanan <venkatan@qti.qualcomm.com>
Signed-off-by: Himateja Reddy <hmreddy@codeaurora.org>
This needs to be explicitly added to the new slumber entry sequence
for gmu and rgmu based targets.
Change-Id: I582067d065b1c58cab3d1d149292dd94e182bd66
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
There can exist a race where we clear the A6XX_RBBM_INT_0_MASK
register while the gpu is going into IFPC. Fix this by clearing this
register before clearing the OOB.
Change-Id: I08e9dbccbfdbee93ba7ef35fbbc673938ee033da
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
This ensures that dcvs runs while the gpu is still actively working
on the same submission for longer than the idle timer.
Change-Id: I85f2ff21dc19a9e589d6ed918bebea4c42b2a39d
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
This property is used to enable dcvs or disable both dcvs and slumber
using kgsl power state transitions. Since gmu or rgmu based targets
don't use the power states, add and use gmu core flag to enable and disable
slumber for those targets.
Change-Id: Iace3af9427c7b84509c9041604972cf14e7cd675
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
