Fixes in qseecom driver to support shmbridge and
change parameters as hypervisor expects them to
be.
Change-Id: I57dc5d6fe7b74b45da2dee6de32c1251d77275ee
Signed-off-by: Anmolpreet Kaur <anmolpre@codeaurora.org>
Enable sharing of pmu counters between kernel clients for the
QGKI images of lahaina and holi.
Change-Id: I1f4ab232f78a37737f9110c7155a4443c8243ece
Signed-off-by: Kaushal Kumar <kaushalk@codeaurora.org>
Its maximal load is about 20mA, so change it by measure.
Change-Id: I1184ac5db5aa067a10cb0accbfda3da7111b4fc3
Signed-off-by: Fei Mao <feim1@codeaurora.org>
Currently if qti_flash_lmh_mitigation_config() returns an error
in qti_flash_led_strobe(), spin_unlock() is not called in the
error return path. Fix it.
Fixes: 42bdecad7c ("leds: qti-flash: Fix LMH mitigation configuration")
Change-Id: I1bede93873a151cc9bab7f2000d8f058e1890fda
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
Currently I/O requests could be still submitted to UFS device while
UFS is working on shutdown flow. This may lead to racing as below
scenarios and finally system may crash due to unclocked register
accesses.
To fix this kind of issues, in ufshcd_shutdown(),
1. Use pm_runtime_get_sync() instead of resuming UFS device by
ufshcd_runtime_resume() "internally" to let runtime PM framework
manage and prevent concurrent runtime operations by incoming I/O
requests.
2. Specifically quiesce the SCSI device of UFS Device well known LU
so that ufshcd_suspend() can still send the SSU cmd, and remove
all the other SCSI devices to block all I/O requests to those
SCSI devices.
Example of racing scenario: While UFS device is runtime-suspended
Thread #1: Executing UFS shutdown flow, e.g.,
ufshcd_suspend(UFS_SHUTDOWN_PM)
Thread #2: Executing runtime resume flow triggered by I/O request,
e.g., ufshcd_resume(UFS_RUNTIME_PM)
This breaks the assumption that UFS PM flows can not be running
concurrently and some unexpected racing behavior may happen.
Change-Id: I83345e6b48a832ec7962fc016f4fdf128c9a5bd1
Signed-off-by: Can Guo <cang@codeaurora.org>
Send SMMU IOVA range to Firmware only when SMMU S1 stage is
enabled.
Change-Id: I3d0d0b6ad3db18aded0d921f79337cf845ceb5f4
Signed-off-by: Naman Padhiar <npadhiar@codeaurora.org>
Add backend user count check to protect the index
boundary.
Change-Id: Ic1b61d1f7130252cc54da0b16553858714988dbd
CRs-Fixed: 2009216
Signed-off-by: Walter Yang <yandongy@codeaurora.org>
This reverts commit 0d5d9413a6 as it
breaks ramdump debug tools. Will bring this back in after resolving
those issues.
Bug: 163100336
Change-Id: Ic64214c63ecd6347f5707cc7354e6969d3af0320
Signed-off-by: Saravana Kannan <saravanak@google.com>
Git-commit: ae8f7f7807
Git-repo: https://android.googlesource.com/kernel/common/
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
This reverts commit 314ac273f0 as it
breaks ramdump debug tools. Will bring this back in after resolving
those issues.
Bug: 163100336
Change-Id: Ibf46f6db0fa2bf9cc9e7121115889e15ca07cdab
Signed-off-by: Saravana Kannan <saravanak@google.com>
Git-commit: d837f090a6
Git-repo: https://android.googlesource.com/kernel/common/
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
This change is for general scheduler improvement.
Change-Id: If6e38ac379564fa906ff3db6be8bee77fcde0478
Signed-off-by: Shaleen Agrawal <shalagra@codeaurora.org>
Currently, the PIL driver expects the debug cookie for disabling
the check for subsystem bootup timeouts in the PIL's standard
IMEM location. However, since the bootloader also loads the firmware,
it's possible that it can use this location to set the cookie that's
needed for ramdump parsers. As a result, the original timeout cookie,
that's usually set before bootloader even begins, is overwritten.
Hence, move the timeout cookie to a different location to avoid this
conflict.
Change-Id: I2e368e9fbd7e996e2a4290b75818fae8cb9277be
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
Mark the scratch buffer as privileged so that it can only be accessed by
GPU through the ringbuffer. To accomplish this, we need to:
1. Disable the shadow rptr feature.
2. Trigger RPTR update from GPU using a WHERE_AM_I packet.
3. Add support for the new ucode.
Change-Id: I9b388f55f53b69028b9bbb2306cb43fd1297c52f
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
a5xx and a6xx both have a need for a bit of scratch memory for preemption.
Rename the existing "counters" member in struct adreno_preemption from a5xx
and use it for a6xx to store the context restore address.
Change-Id: Ic0dedbad6493e99b35d8c771673e8f9f686f927c
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Enable shmbridge on lahaina and change parameters
to make it inline with what hyp expects. This
change introduces a support_hyp flag to indicate
if hypervisor support is available for target and
change the parameters accordingly.
Change-Id: If17ece63de719105e0c1de53f5408ec6f462ba13
Signed-off-by: Anmolpreet Kaur <anmolpre@codeaurora.org>
Set flush cti for both etr and etb. Set FlushandStop bit to default
value of FFCR in enablement function. Config the correct trigger number
of flush and reset cti for both etr and etb.
Change-Id: Idee3802e5a69aca521a6259f9936ddb8361a87d4
Signed-off-by: Tao Zhang <taozha@codeaurora.org>
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
setup_fifo_xfer/setup_gsi_xfer api may fail while transfer
preparation, return error to the client in such case instead
of advancing with the erroneous transfer to prevent unpredictable
transfer scenarios.
Change-Id: I559fbc1dd26248c639cd0f0e1844dafbada703ce
Signed-off-by: Mukesh Kumar Savaliya <msavaliy@codeaurora.org>
For I2C and SPI, CMD_DONE should be enabled only in fifo mode for
transfer completion. Disable CMD_DONE for DMA mode and cancel cmd
to avoid race condition between cmd_done, dma_done and cmd_done,
cancel_irq.
Change-Id: Ib1dc10d3e17c2b3df17097f2a4bc60b159d76709
Signed-off-by: Mukesh Kumar Savaliya <msavaliy@codeaurora.org>
Reinitialize fifo cur_wr, cur_rd and gi2c->xfer for every transfer.
Add "MSM_GPI_QUP_FW_ERROR" event to callback event list. Dump GSI
registers in case of Channel RESET failure.
Change-Id: I243fb140d663fccd79676bdc6760702809fb4d68
Signed-off-by: Mukesh Kumar Savaliya <msavaliy@codeaurora.org>
Signed-off-by: Vipin Deep Kaur <vkaur@codeaurora.org>
This is a squash of the following two commits taken from msm-4.14
1) commit <e629221afd65> ("Perf: core: create/delete shared
kernel events").
Frequently drivers want to monitor some event like L2 misses
and cycles+instructions. If more than 1 driver wants to monitor
the same event and the event attributes are the same then we
can create just one instance of the event and let drivers
share the event. Add shared event create and delete
routines.
2) commit <f0453c73e167> ("perf: Add support for user and
kernel event sharing").
The ARM PMU counters are limited in number. Even for counting
similar events, the PMU driver allocates a new counter. Hence,
counters configured to count similar events are shared. This
was only possible for the kernel clients, but not for user-space
clients. Hence, as an extension to this, the kernel and the
user-space are now able to share the similar events. The counters
can be shared between user-space only clients, kernel only clients,
and among user-space and kernel clients. The kernel and user's
attr->type (hardware/raw) and attr->config should be same for them to
share the same counter.
Additionally,
Current enablement of kernel event sharing is not GKI
compliant. Make the sharing of kernel events configurable
so it can be enabled only on non-GKI builds.
Add dependency for enablement of sharing of user events on
enablement of sharing of kernel events.
Change-Id: I784db5a20968ba7fca20659186f23890bf6cc503
Signed-off-by: Patrick Fay <pfay@codeaurora.org>
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
[kaushalk@codeaurora.org: Make event sharing configurable, add dependencies]
Signed-off-by: Kaushal Kumar <kaushalk@codeaurora.org>
Update the DMA RX FSM reset sequence as per HPG recommendations.
Currently driver calling msm_geni_serial_rx_fsm_rst() even in case of
RX inactive. RX FSM reset command generates RX_RESET_DONE bit. There
is a possible race between polling for RX_RESET and ISR for RX_RESET.
This can result into introducing delay during BT open.
Fix this by updating RX FSM reset sequence only in case of
cancel command timeout.
Change-Id: I90532aa72fdad462a616eded3e149bc6b721fe7b
Signed-off-by: Chandana Kishori Chiluveru <cchiluve@codeaurora.org>
CVP firmware may crash if releasing non-existent ARP buffer.
Change-Id: Ia1d6a5d28c115a7ff22d68b698e0b3e560828c35
Signed-off-by: George Shen <sqiao@codeaurora.org>
In some error scenarios, adequate information is not obtained
from the debug registers dump as by the time the table of
registers reaches BHI error registers, the link state has gone
bad. Prioritize those BHI error registers so that they come up
first in the list of registers to dump upon any error scenario.
Change-Id: I0488cf05a04fb974984f91fe9a67c8e12f8309c7
Signed-off-by: Bhaumik Bhatt <bbhatt@codeaurora.org>
With CPU re-ordering on write instructions, there might
be a chance that the HWO is set before the TRB is updated
with the new mapped buffer address.
And in the case where core is processing a list of TRBs
it is possible that it fetched the TRBs when the HWO is set
but before the buffer address is updated.
Prevent this by adding a memory barrier before the HWO
is updated to ensure that the core always process the
updated TRBs.
Change-Id: Idc008b2d4e37dd0c10c8ae40ab5af1ffd0775877
Signed-off-by: Sriharsha Allenki <sallenki@codeaurora.org>
Protect remote heap buffer list with spin lock while freeing
to avoid UAF in fastrpc_mmap_find() on a buffer that is freed
in fastrpc_mmap_free().
Change-Id: Ic3d5219898fcf23fb813eabe5fc2f187b397a472
Acked-by: Chenna Kesava Raju <chennak@qti.qualcomm.com>
Signed-off-by: Jeya R <jeyr@codeaurora.org>
* refs/heads/tmp-3f413d0:
Linux 5.4.57
bpf: sockmap: Require attach_bpf_fd when detaching a program
selftests: bpf: Fix detach from sockmap tests
ext4: fix direct I/O read error
arm64: Workaround circular dependency in pointer_auth.h
random32: move the pseudo-random 32-bit definitions to prandom.h
random32: remove net_rand_state from the latent entropy gcc plugin
random: fix circular include dependency on arm64 after addition of percpu.h
ARM: percpu.h: fix build error
random32: update the net random state on interrupt and activity
ANDROID: Update ABI xml
UPSTREAM: of: property: Add device link support for pinctrl-0 through pinctrl-8
UPSTREAM: of: property: Add device link support for multiple DT bindings
UPSTREAM: of: property: Add device link support for extcon
UPSTREAM: driver core: Change delimiter in devlink device's name to "--"
UPSTREAM: driver core: Fix sleeping in invalid context during device link deletion
BACKPORT: driver core: Add waiting_for_supplier sysfs file for devices
UPSTREAM: driver core: Add state_synced sysfs file for devices that support it
UPSTREAM: driver core: Expose device link details in sysfs
UPSTREAM: driver core: Avoid deferred probe due to fw_devlink_pause/resume()
UPSTREAM: driver core: Rename dev_links_info.defer_sync to defer_hook
UPSTREAM: driver core: Don't do deferred probe in parallel with kernel_init thread
UPSTREAM: arm64/module: Optimize module load time by optimizing PLT counting
FROMGIT: scsi: block: pm: Simplify resume handling
Change-Id: Ide67c767b3a0f455ab5cec4b571ab599eae813d5
Signed-off-by: Blagovest Kolenichev <bkolenichev@codeaurora.org>
Update DDR_CONFIG register with HSR value if HSR value is supplied
in the device tree.
Change-Id: Ia811eaf48b4ef6af39dc882ac498bf88436e2f4b
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
SDHC core with new 14lpp and later tech DLL should not enable
PWRSAVE_DLL since such controller's internal gating cannot meet
following MCLK requirement:
When MCLK is gated OFF, it is not gated for less than 0.5us and MCLK
must be switched on for at-least 1us before DATA starts coming.
Adding support for this requirement.
Change-Id: I571c8fb40835e094d8feb4df5c2d049c02a0a2f2
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
Reviewed-by: Can Guo <cang@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/1581077075-26011-1-git-send-email-vbadigan@codeaurora.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
If eMMC is not a primary bootdevice, there isn't any point of probing
eMMC device hence disable the probing in such case.
Change-Id: I67a025606b03bb3cc21e818c2b4b519aa2b53888
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
Update the LLCC SCT table for Shima for clients to request
slices from system cache.
Change-Id: Ia72539129e4b81f6807d97f5ac091636d67278d1
Signed-off-by: Mukesh Ojha <mojha@codeaurora.org>
Add cpu util trace point in RT EAS task placement decisions to
help debug RT taskplacement issues.
Change-Id: Ib79484e1bef863a634507989fda577ca2f79020b
Signed-off-by: Lingutla Chandrasekhar <clingutla@codeaurora.org>
This change is for general scheduler improvement.
Change-Id: I7da1c3cff4fb9470a3904407f180463c26315e68
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
This patch adds the logic to forward the irq type from
the mpm irq domain to its parent gic irq domain.
Change-Id: Id7c42ba59e0d003ffaa0a7951be4a2d3ffdb64a4
Signed-off-by: Raghavendra Kakarla <rkakarla@codeaurora.org>
