Commit graph

883,859 commits

Author SHA1 Message Date
qctecmdr
9db02bb1ad Merge "msm: rdbg: Add snapshot of remote debugger driver" 2020-05-26 09:46:02 -07:00
qctecmdr
89194b4b74 Merge "msm: kgsl: Use DMA APIs for cache operations" 2020-05-26 09:46:02 -07:00
qctecmdr
7dbb2a281f Merge "msm: cvp: handles dsp error more reliably" 2020-05-26 09:46:02 -07:00
qctecmdr
113813fd26 Merge "arm: make default iova alignment as 2mb" 2020-05-26 05:19:43 -07:00
qctecmdr
f32b8945f0 Merge "clk: qcom: camcc: Add support for CAMCC clock driver for SHIMA" 2020-05-26 01:31:01 -07:00
Mohammed Nayeem Ur Rahman
fac21defed msm: rdbg: Add snapshot of remote debugger driver
The Remote Debugger driver allows a debugger running
on a host PC to communicate with a remotestub running
on peripheral subsystems.
This snapshot was taken as of msm-3.10 commit
("Merge "msm: msm_bus: Provide valid input pointer argument").

Change-Id: Id79ca428b311dda90467155611af3e2a0fff1fcf
Acked-by: Devender Kaushik <dkaushik@qti.qualcomm.com>
Signed-off-by: Mohammed Nayeem Ur Rahman <mohara@codeaurora.org>
2020-05-26 12:50:12 +05:30
Himateja Reddy
2a7519b146 msm: adsprpc: remove exsessive logging in context_free
Async RPC can easily exhaust the context table and results in failure.
Context free during context table exhaustion failure causes excessive
logging. Remove logging in context_free.

Change-Id: I4de2d638d465f98eeccabaefe99ae589e3780169
Signed-off-by: Himateja Reddy <hmreddy@codeaurora.org>
2020-05-25 18:57:01 -07:00
qctecmdr
729fffbd95 Merge "arm: dma_mapping: Support for DOMAIN_ATTR_S1_BYPASS attribute" 2020-05-25 06:14:50 -07:00
qctecmdr
4c41069d14 Merge "soc: qcom: spss_utils: fix driver module remove" 2020-05-25 06:14:50 -07:00
qctecmdr
81604f60ff Merge "coresight: tmc: set buffer size to 32MB on SW USB mode" 2020-05-25 06:14:49 -07:00
qctecmdr
54734c6f24 Merge "coresight: etm4x: call cpus_read_unlock in error exit" 2020-05-25 06:14:49 -07:00
qctecmdr
b6f208ddff Merge "clk: qcom: gcc-shima: Add support for ref clocks" 2020-05-25 06:14:48 -07:00
qctecmdr
8502acac7a Merge "input: touchscreen: st: fix security issue" 2020-05-25 02:30:40 -07:00
Charan Teja Reddy
bb7d10aa8e arm: make default iova alignment as 2mb
To get the 2MB aligned IOVA section mappings, set
ARM_DMA_IOMMU_ALIGNMENT to 9.

Change-Id: I3254c39e4864c32d6f25a4d416b1b7aec6756ecd
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:27:30 -07:00
Shiraz Hashim
61311e5672 arm: provision page alloc debug support
Equip arm to support ARCH_SUPPORTS_DEBUG_PAGEALLOC and
enable it by default.

Having this support means all pages freed at buddy level
would be marked as read-only and would help catch any
scribbling over free page area. Allocated pages mapping
attributes is restored to read/write.

ARCH_SUPPORTS_DEBUG_PAGEALLOC needs FORCE_PAGES which
ensures all kernel mapping are populated with page
granularity and it would ensure page level accesses  can
be rightly configured.

Change-Id: I9b23d1fb0b9594cc148b082c104da9a773c26057
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:26:24 -07:00
Shiraz Hashim
629471283e arm: mm: program ptes for access restriction
CONFIG_RODATA allows strict kernel mapping permissions to
be followed and accordingly maps regions as read-only,
not-executable etc. correspondingly. CONFIG_RODATA however
assumes all memory regions to be SECTION_SIZE aligned and
section mapped for performance reasons.

With CONFIG_FORCE_PAGES, we force all kernel mappings as
page mapped thus breaking CONFIG_RODATA.

Provide provision to apply permissions at page (pte)
level, if CONFIG_RODATA does not find section mapping.

Change-Id: I8dbf5c3741836bc63a231d8a471cf0306662993b
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:26:01 -07:00
Liam Mark
b4aefd26a7 arm: dma-mapping: handle IOVA address zero
The IOVA allocator used by these calls supports IOVA address
zero so properly handle IOVA address zero.

Change-Id: Iaaad45b42503f05f95d1333e010f6d8e3bdb1949
Signed-off-by: Liam Mark <lmark@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:25:21 -07:00
Chintan Pandya
832decaf00 arm: dma-mapping: map sg lists into the SMMU as virtually contiguous
In arm_iommu_map_sg, currently we map each individual link in the given
scatterlist into the SMMU individually such that they may or may not be
virtually contiguous.  However, in most of our use cases we
actually want the entire sg list mapped into the SMMU as a single
contiguous range.

This was missing for arm 32bit, add it.

Change-Id: Ibf67f29a60b8d19e526c4719590f2f473ea9dca5
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:24:44 -07:00
Laura Abbott
de79fc71ee arm: dma: Expand the page protection attributes
Currently, the decision on which page protection to use
is limited to writecombine and coherent. Expand to include
non consistent memory.

Change-Id: I7585fe3ce804cf321a5585c3d93deb7a7c95045c
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:23:08 -07:00
Shiraz Hashim
ae9f381057 arm: keep address range pmd aligned while remap
During early init, all dma areas are remapped to PAGE_SIZE
granularity. Since full pmd regions are cleared to be
remapped into PAGE_SIZE, ensure that address range is pmd
size aligned while not crossing memory boundaries.

This would ensure that even if address region is not pmd
aligned, its mapping would not be cleared but factored in to
PAGE_SIZE regions.

Change-Id: Iad4ad7fd6169cdc693d532821aba453465addb7c
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:22:49 -07:00
Shiraz Hashim
dd1e256440 arm: mm: consider only lowmem regions while remap
Consider only those memory blocks with lowmem while
remapping into 4KB regions using CONFIG_FORCE_PAGES
feature.

Change-Id: Ie209fce6c310f911d8cf02d977e226660684a6ab
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:11:18 -07:00
Shiraz Hashim
848bfb6423 arm: mm: fix pte allocation with CONFIG_FORCE_PAGES feature
CONFIG_FORCE_PAGES introduces a debug option to mark free
pages as read only in order to trigger a fault if any code
attempts to write to a page on the buddy list.

In order to achieve this it splits all section mappings in
to PAGE_SIZE pages during boot. While doing this split, it
wrongly allocates a pte (of page size) for each pmd. Linux
however in armv7 short descriptor format, uses same second
level pte for 2 consecutive pmds offset by the actual second
level table size. Refer comments in kernel file
arch/arm/include/asm/pgtable-2level.h for details.

Fix this by allocating pte for a section mapped pmd while
providing required offset if pte already exists.

Change-Id: Iadbaa5e71e4b220208a7275bf039a2a413349e42
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:10:57 -07:00
Laura Abbott
cec36b1c9c arm: Allow remapping lowmem as 4K pages
Lowmem is currently mapped with sections (1MB/2MB) whenever
possible due to TLB performance boosts. Sections cannot easily
be changed at runtime however which makes implementing certain
features annoying. Add an option to map lowmem with 4K patches.
This is intended to be used as a debugging feature and should
NOT be used for performance testing.

Change-Id: I9612a99b8e05a022f5ba7e568f21307cf66b5667
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Susheel Khiani <skhiani@codeaurora.org>
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-25 00:10:39 -07:00
Qingqing Zhou
85b0f9f9f7 arm: dma-mapping: add dma mapper for io-pgtable-fast for 32 bit
io-pgtable-fast was implemented to achieve
better performance for IOMMU map/un-map. Add
DMA API support that goes through io-pgtable-fast
for 32 bit targets.

Change-Id: I3d0560a4331f6b7b87c70d0885df11d12cb1d6ec
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
[qqzhou@codeaurora.org: Reorganize codes to be more clear]
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-24 23:59:04 -07:00
Qingqing Zhou
020939113f arm: dma_mapping: Support for DOMAIN_ATTR_S1_BYPASS attribute
For iommus which do not use stage1 translation, stage2 may not be aware
of the device's dma_mask requirements. Choose the dma_ops such that
allocations are made within the dma_mask region and bounce buffers are
used as necessary.

Change-Id: I63ae3ff9e5ab608892d12db7a813264d234699ee
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-24 23:58:32 -07:00
Qingqing Zhou
b1cce515d1 arm: dma-mapping: Use default iommu domain
When a device probes and arch_setup_dma_ops is called, check if the
device has an associated default iommu_domain. If it does, setup
a virtual address allocator of the type described by the
default domain's attributes.

Mark arm_iommu_create_mapping and arm_iommu_attach_device as
deprecated, since clients will no longer need to use them now that
the iommu framework will associate them with a default domain.

Change-Id: I0721c038c68f0f48b78d50f9a72418dbaed97172
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
Signed-off-by: Qingqing Zhou <qqzhou@codeaurora.org>
2020-05-24 23:56:38 -07:00
Fei Mao
03b0844fcd input: touchscreen: st: fix security issue
Set correct parameter for the function 'strlcpy' and avoid kernel panic.

Change-Id: I8bf76da6022df43b630d5e66022892eadc662871
Signed-off-by: Fei Mao <feim1@codeaurora.org>
2020-05-24 22:50:50 -07:00
Konstantin Dorfman
e63f3e7c16 soc: qcom: spss_utils: fix driver module remove
.remove need to remove apps_cmac attribute.

Change-Id: Ic636ee707e831d67059841f1d59cc00e9149ce8c
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
2020-05-24 12:22:22 -07:00
Konstantin Dorfman
f1db625450 soc: qcom: spcom: pr_fmt to print function name
CTS failed on Lahaina due to absence of function name in the driver print.
This change adds function name to each driver print.

Change-Id: I2603c460e77578e7a56553a92058cc1b463c11c0
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
2020-05-24 12:21:42 -07:00
qctecmdr
4a2732a964 Merge "Revert "SoC: soc-pcm: call pcm_new when creating new pcm"" 2020-05-24 07:08:37 -07:00
Jagadeesh Kona
b9289ce979 clk: qcom: camcc: Add support for CAMCC clock driver for SHIMA
Add support for Camera clock controller driver for the camera
clients to be able to control clocks.

Change-Id: I6aa7a2887ece1fb80d24242d4b6ea37519e4bb3c
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
2020-05-24 12:26:28 +05:30
Jagadeesh Kona
f6eaf2f2ed dt-bindings: clock: Update clock ids and BCRs of CAMCC and GPUCC for SHIMA
Update the clock ids and BCRs of Camera and Graphics Clock Controller
for SHIMA.

Change-Id: Ie1a360bd247c0f9e74b15c47677f4cef5f8c7a80
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
2020-05-24 12:25:58 +05:30
qctecmdr
bd555ae76a Merge "leds: qti-flash: Limit off_time of switch to a maximum of 1280 ms" 2020-05-23 16:46:19 -07:00
qctecmdr
e3e3bd297b Merge "mmc: Enable SD card clock scaling" 2020-05-23 00:47:17 -07:00
qctecmdr
e9ea3e9a6b Merge "dwc3: Remove check for HWO flag in dwc3_gadget_ep_reclaim_trb_sg()" 2020-05-22 20:32:57 -07:00
qctecmdr
f3ac7df1a8 Merge "haven: Fix compilation error when DEBUG_FS is disabled" 2020-05-22 20:32:57 -07:00
qctecmdr
928682665b Merge "soc: qcom: mem-buf: Limit the number of input ACL entries" 2020-05-22 20:32:57 -07:00
Bao D. Nguyen
ef59869dfe mmc: Enable SD card clock scaling
The SD card clock scaling feature has a dependency on the
MMC_SDHCI_MSM which is not defined. Remove this dependency
so that the SD card clock scaling feature can be enabled.
In addition, fix the SD cards 2.0 initialization caused
by the incorrect clock settings.

Change-Id: I3eaec3546f89b86643b1937764288b3f39578c0e
Signed-off-by: Bao D. Nguyen <nguyenb@codeaurora.org>
2020-05-22 16:30:56 -07:00
qctecmdr
c48bd2c6e7 Merge "Revert "ALSA: jack: Add support to report second microphone"" 2020-05-22 16:30:14 -07:00
qctecmdr
76eff845b4 Merge "firmware: qcom_scm: Pass arginfo for sec_wdog_trigger" 2020-05-22 16:30:13 -07:00
qctecmdr
aa259d599a Merge "trace: msm_low_power: update text description" 2020-05-22 16:30:13 -07:00
qctecmdr
07b4fed769 Merge "nvmem: core: Export nvmem cell info to userspace" 2020-05-22 16:30:12 -07:00
qctecmdr
32b9fcd606 Merge "usb: dwc3: gadget: Give back staled requests" 2020-05-22 16:30:12 -07:00
qctecmdr
fe64ebf9ac Merge "msm: adsprpc: Print and return appropriate error codes" 2020-05-22 16:30:11 -07:00
qctecmdr
3116e4c12a Merge "msm: kgsl: Add support for A619 GPU variant" 2020-05-22 16:30:10 -07:00
Isaac J. Manjarres
0d121e6dc3 soc: qcom: mem-buf: Limit the number of input ACL entries
The number of ACL entries is currently not sanitized, which
can allow for unreasonably large ACL to be allocated for
later processing. Allowing for this to happen doesn't make much
sense, as there aren't any valid usecases that require a large
ACL, so restrict the number of ACL entries to 16. Also, while we're
here, fix up some of the error handling in a few places.

Change-Id: I5d1371ed180608486bcde1e208a36782986313af
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-05-22 14:17:56 -07:00
Isaac J. Manjarres
75455dfc54 soc: qcom: mem-buf: Fix message queue registration check
The condition that determines if we print an error after
failing to register for the mem-buf message queue checks
the return code against EPROBE_DEFER. This is not correct, as
error codes are negative, so fix the check.

Change-Id: I4ed03bde56c6edf66e0ffed060ec23a87a46be54
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-05-22 14:12:13 -07:00
qctecmdr
c6886a4d66 Merge "Makefile: Add a check of CONFIG_TRIM_UNUSED_KSYMS before remaking vmlinux" 2020-05-22 12:06:22 -07:00
Isaac J. Manjarres
ca3e7ebe4f soc: qcom: mem-buf: Configure the mem-buf device's DMA mask
The mem-buf device can handle memory from anywhere in the
system. This includes memory with a physical address above
32 bits, so configure the DMA mask for the mem-buf device
based on the system configuration.

Change-Id: If91bb6d8044e8e6f47994acd7e50633b46596808
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-05-22 11:10:58 -07:00
George Shen
f4d49c6800 msm: cvp: handles dsp error more reliably
In case DSP failed to respond to CPU command correctly, cvp driver
shall ignore the DSP error other than print error message. It shall
keep working normally.

Change-Id: Id33c0063b6326bc45527e2b4d60584045ca1e07c
Signed-off-by: George Shen <sqiao@codeaurora.org>
2020-05-22 10:20:21 -07:00