Probing the ID registers and setting up the SMMU configuration is an
area where overrides and workarounds may well be needed. Indeed, the
Cavium workaround detection lives there at the moment, so let's break
that out.
Change-Id: I2b828a98981866a1a5adf21555055b8a4c9788d2
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Git-commit: 3995e18689
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[isaacm@codeauora.org: resolve trivial merge conflicts]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Move detection of the Secure access quirk to its new home, trimming it
down in the process - time has proven that boolean DT flags are neither
ideal nor necessarily sufficient, so it's highly unlikely we'll ever add
more, let alone enough to justify the frankly overengineered parsing
machinery.
Change-Id: I86a898715cb1d036949df4dcf7333068bcf64836
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Git-commit: 6d7dff62af
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[isaacm@codeaurora.org: resolved merge conflicts]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Add some nascent infrastructure for handling implementation-specific
details outside the flow of the architectural code. This will allow us
to keep mutually-incompatible vendor-specific hooks in their own files
where the respective interested parties can maintain them with minimal
chance of conflicts. As somewhat of a template, we'll start with a
general place to collect the relatively trivial existing quirks.
Change-Id: Ie1ee37e9250a8295bc07cb78d879b98452f50920
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Git-commit: fc058d37b3
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[isaacm@codeaurora.org: resolved merge conflics and build errors]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
We're about to start using it for more than just register definitions,
so generalise the name.
Change-Id: I15630ae6f50ce8c10a624542038275861608174d
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Git-commit: c5fc64881f
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Clean up the remaining accesses to GR0 registers, so that everything is
now neatly abstracted. This folds up the Non-Secure alias quirk as the
first step towards moving it out of the way entirely. Although GR0 does
technically contain some 64-bit registers (sGFAR and the weird SMMUv2
HYPC and MONC stuff), they're not ones we have any need to access.
Change-Id: I254eef03e4350fc2abf60547e860c5c65cedafc4
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Git-commit: 00320ce650
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[isaacm@codeaurora.org: resolved merge conflicts/build errors]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Context bank accesses are fiddly enough to deserve a number of extra
helpers to keep the callsites looking sane, even though there are only
one or two of each.
Change-Id: I4ec6ce09eae4c41d228086b15574c3e9e816f552
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Git-commit: 19713fd40d
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[isaacm@codeaurora.org: resolved merge conflicts/build errors]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Introduce some register access abstractions which we will later use to
encapsulate various quirks. GR1 is the easiest page to start with.
Change-Id: I2dfb3a12ebcb705874f75799ec6f1997abf488ff
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Git-commit: aadbf2143a
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[isaacm@codeaurora.org: resolved merge conflicts/build errors]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
The smmu_write_atomic_lq oddity made some sense when the context
format was effectively tied to CONFIG_64BIT, but these days it's
simpler to just pick an explicit access size based on the format
for the one-and-a-half times we actually care.
Change-Id: I5b4ca8162c801aa320576ff3d31bb20acca9b1f8
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Git-repo: 6100576284
Git-commit: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[isaacm@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Since we now use separate iommu_gather_ops for stage 1 and stage 2
contexts, we may as well divide up the monolithic callback into its
respective stage 1 and stage 2 parts.
Change-Id: I566d03bd7941baedcbc2345ffdeefcb4041e9b54
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Git-commit: 71e8a8cdaf
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[isaacm@codeaurora: resolved trivial merge conflicts]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
To keep register-access quirks manageable, we want to structure things
to avoid needing too many individual overrides. It seems fairly clean to
have a single interface which handles both global and context registers
in terms of the architectural pages, so the first preparatory step is to
rework cb_base into a page number rather than an absolute address.
Change-Id: I2401a30f38550823a60421355d73c4306d0613ed
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Git-commit: 490325e0c1
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[isaacm@codeaurora.org: resolve trivial merge conflicts]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Finish the final part of the job, once again updating some names to
match the current spec.
Change-Id: I405fa064194b5c90b13935fb37b36ba9e8ee35c0
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Git-commit: 620565a76b
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[isaacm@codeaurora.org: resolved merge conflicts/build time errors]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
As for GR0, use the bitfield helpers to make GR1 usage a little cleaner,
and use it as an opportunity to audit and tidy the definitions. This
tweaks the handling of CBAR types to match what we did for S2CR a while
back, and fixes a couple of names which didn't quite match the latest
architecture spec (IHI0062D.c).
Change-Id: Ic6833f472f162ab6080aaba37b8259e573436a65
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Git-commit: 5114e96cb2
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[isaacm@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
FIELD_PREP remains a terrible name, but the overall simplification will
make further work on this stuff that much more manageable. This also
serves as an audit of the header, wherein we can impose a consistent
grouping and ordering of the offset and field definitions
Change-Id: I3935f9f9b7526cb5c5906093131e856159b0899b
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Git-commit: 0caf5f4e84
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[isaacm@codeaurora.org: resolved merge conflicts/build errors]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
The arm_smmu_power_off_atomic() function derives the pointer to
the SMMU device by incorrectly assuming that all devices in the
power resources structures store that pointer as part of their
driver data.
While this is true for devices that represent an SMMU, this is
not the case for the devices that represent the TBUs, as they
store the TBU structures instead of a pointer to the SMMU device.
Thus, require the SMMU device as a parameter to the
arm_smmu_power_off[_atomic] functions so that it can be used
correctly.
Change-Id: I0101500468afe17456bd6178082850e5fa6590d7
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Adding a function to check for dangling pointer using IPA IDR structure
to avoid use after free error.
Change-Id: I0bd3d733bf10403366abc643f89c3e5c5e6228e9
Acked-by: Suhas Mallesh <smallesh@qti.qualcomm.com>
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
Introduce a new domain for wakeup capable GPIOs. The domain can be
requested using the bus token DOMAIN_BUS_WAKEUP. In the following
patches, we will specify PDC as the wakeup-parent for the TLMM GPIO
irqchip. Requesting a wakeup GPIO will setup the GPIO and the
corresponding PDC interrupt as its parent.
Change-Id: I13b206773e5f04452eed87ad1490da50b034ac4c
Co-developed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Change the if condition to be inclusive to allow remove_offload
ioctl to send the rmv_offload_request through qmi on the last
connection.
Change-Id: I6eec7799fd1a76ab168bc588b3e9c74dbfd215fd
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
Remove code check-in not belonging to IPA driver.
Change-Id: I6f79d72d054c7c3b9d5448ae83150d5afaedacff
Signed-off-by: Bojun Pan <bojunp@codeaurora.org>
The less said about "~12UL" the better. Oh dear.
We get away with it due to calling constraints that mean IOVAs are
implicitly at least page-aligned to begin with, but still; oh dear.
Change-Id: I8e4ed0ccc1aae76988449895e6f7a9944d429af6
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Git-commit: 353b325047
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Instead of using a symlink to point to the MSM ION header,
place it directly in the include/uapi/linux path.
Change-Id: Id2a91adb4bdfc2c03e8eb535882734603ccd0f94
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
The system secure heap relies on the existence of the system
heap. Thus, if the system heap is not available, do not create,
the system secure heap.
Change-Id: I7a99e0fda45ae02ed6e5c8a797d29e917e84f182
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
KW tool detect the potential NULL access and buffer
index overflow issue.
The change is to add the proper handle for NULL response
and prevent buffer index overflow.
Change-Id: I0bb1b45ba6e5b0abe6c3539d451f74e19028737c
Signed-off-by: Bojun Pan <bojunp@codeaurora.org>
This fix enables HOLB drop timeout for MHIP TX channels which will
cause IPA to drop the packets if the packet is not processed within
the timeout. This will help relieve the back pressure on MHIP Producer
channels.
Change-Id: I607ebb460c970ccbcce2f0e364ff22e0222ded03
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
There is a possibility to access coal registers when the clock
is off which results in unknown behavior. Make changes to ensure
clock is on when accessing coal registers.
Change-Id: Ia13841c5543798cb47ed6953a5c714e7426cb180
Signed-off-by: Chaitanya Pratapa <cpratapa@codeaurora.org>
During device reboot when IPA is going for shutdown,
the allocation for memory request fails. Add change in
IPA to not sleep while memory allocation.
Change-Id: I0bdbf0f622770566ad1135c76f6edc2790285420
Signed-off-by: Pooja Kumari <kumarip@codeaurora.org>
While freeing the buffers in the transfer ring, the ref_count of the
pages that were allocated from the sys->repl->cache have to be
decremented explicitly to ensure there is no memory leak.
Change-Id: Ie853bf15f084f503e8818d46c72671dbb9ddad7b
Acked-by: Priyadarshini Rajagopal <prajagop@qti.qualcomm.com>
Signed-off-by: Bojun Pan <bojunp@codeaurora.org>
db_timer expires after wq has been flushed in ipa3_teardown_sys_pipe.
This causes the wq to be scheduled after pipe teardown.
Add workqueue_flushed flag which set after the wq is flushed during
teardown. This flag is checked against in the wq function to ensure
it is not executed once the wq has been flushed.
Change-Id: I176a3a6dbf25985a41decf008ad045647081b871
Acked-by: Priyadarshini Rajagopal <prajagop@qti.qualcomm.com>
Signed-off-by: Bojun Pan <bojunp@codeaurora.org>
Enable USB-DPL ep on MHI configuration
which was missed.
Change-Id: I881696d0fb383e7644670e7c2940022433069a8c
Signed-off-by: Mohammed Javid <mjavid@codeaurora.org>
Update the bonus ways for the MMUHWT entry of the SCT table
as per the new configuration.
Change-Id: I144290b7b0c1e5781842d1034d5084566a180df6
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
Add enum for QMI_ERR_DISABLED_V01 for clients to use in the kernel.
Previously, this error enum was not used by any client but the service
registry service has updated to use this enum.
Change-Id: I955b3d6f1acf2e5cfb2627323f6b0662810834ae
Signed-off-by: Chris Lew <clew@codeaurora.org>
When default wan consumer pipe polling mode was changed, not updating
the polling mode for coalescing pipe. As both the pipes are sharing
a common event ring because of that observing warning logs, it was
leading to watchdog bite. Add changes to update the polling mode
for coalescing channel when wan default pipe polling mode changed.
Change-Id: I8630c9866cb7925d21ff7fd9dc68fcb03a98cbc5
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
