Commit graph

884,433 commits

Author SHA1 Message Date
Nitin Rawat
b46eae7dad pinctrl: qcom: Expose ufs_reset as gpio on holi
The ufs_reset pin is expected to be wired to the reset pin of the
primary UFS memory but is pretty much just a general purpose output pin.
Reorder the pins and expose it as gpio 156, so that the UFS driver can
toggle it.

Change-Id: I566196bd2ab6629c2761b47ed844022cf9ffb458
Signed-off-by: Nitin Rawat <nitirawa@codeaurora.org>
2020-06-22 02:47:47 +05:30
qctecmdr
b22d0ea027 Merge "arm64: defconfig: Enable CONFIG_PSI_FTRACE on Lahaina" 2020-06-20 13:12:14 -07:00
qctecmdr
d5bf014032 Merge "sched/walt: Improve the scheduler" 2020-06-20 10:46:39 -07:00
Mayank Rana
37084ff13d dwc3: gadget: Separate out top and bottom half based logging
Currently USB top and bottom half are using same index to update
number of events posted/handled, and updating relevant time. As
top half is not guaranteed to be prevented when bottom half is
running those index based logging doesn't allow to relate information.
Also start logging bh_start_time and increase existing buffer size
from 10 to 25 to get more data of USB interrupt processing.

Also get count how many cancelled requqest being given back from
bottom half context, and log any update/start cmd failure.

Change-Id: Iefc883cb5a2259f256f30c9727db8a68ddd41af7
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
2020-06-19 18:15:41 -07:00
Pavankumar Kondeti
82fea0f9dc sched/walt: Improve the scheduler
This change is for general scheduler improvements.

Change-Id: I80606a09c3d09c65b7bcdf3940bee5e155d6318c
Co-developed-by: Lingutla Chandrasekhar <clingutla@codeaurora.org>
Signed-off-by: Lingutla Chandrasekhar <clingutla@codeaurora.org>
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
[satyap@codeaurora.org: fix trivial merge conflicts]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2020-06-19 10:14:20 -07:00
Pavankumar Kondeti
961c3a5fc3 sched/walt: Improve the scheduler
This change is for general scheduler improvements.

Change-Id: Ica36bb6ccd4c2d8897dab62614eadb5a060d5390
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
2020-06-19 10:14:11 -07:00
Pavankumar Kondeti
d0a6a9b767 sched/walt: Improve the scheduler
This change is for general scheduler improvements.

Change-Id: I5f19453ec1a19c71d67a02c3f0ec9967e7673a4b
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
[satyap@codeaurora.org: fix trivial merge conflicts]
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2020-06-19 10:14:07 -07:00
Pavankumar Kondeti
b1250b5cf6 sched: Improve the scheduler
This change is for general scheduler improvements.

Change-Id: I3a220142f08a9664845b4d0e9918ec7c48bb11f7
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
2020-06-19 10:14:01 -07:00
qctecmdr
04fda4c2c5 Merge "coresight: tpdm: add an option "qcom,cmb-msr-skip" for tpdm" 2020-06-19 09:50:06 -07:00
qctecmdr
61b129b0a6 Merge "taskstats: remove redundant MM_STAT config check" 2020-06-19 09:50:06 -07:00
qctecmdr
e399dc502d Merge "net: qrtr: Add tracepoint support" 2020-06-19 09:50:06 -07:00
qctecmdr
30e36e954d Merge "net: qrtr: haven: Add svm device tree parsing" 2020-06-19 09:50:06 -07:00
qctecmdr
e10b49be7b Merge "coresight: tmc-etr: Fix deadlock issue while reading from ETR" 2020-06-19 09:50:05 -07:00
qctecmdr
6c409bb596 Merge "coresight: byte-cnter: Replace dev_err with ratelimited API" 2020-06-19 09:50:05 -07:00
Isaac J. Manjarres
e0237ca515 arm64: defconfig: Enable CONFIG_PSI_FTRACE on Lahaina
Enable PSI ftrace logging to collect ftrace information about
PSI events.

Change-Id: Ia4d786f5cbc242991fd0e0ecdb63d16714bffeb8
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-06-19 09:41:58 -07:00
Yuanfang Zhang
1f9a3b55de coresight: tpdm: add an option "qcom,cmb-msr-skip" for tpdm
Some tpdm don't support cmb msr, add an option "qcom,cmb-msr-skip"
to indicate whether MSR is supported.

Change-Id: I8ae66e639fe68b236ad8a268b18acbda737a9d93
Signed-off-by: Yuanfang Zhang <zhangyuanfang@codeaurora.org>
2020-06-19 14:00:57 +08:00
qctecmdr
b982c53bc3 Merge "usb: dwc3: trace: print enqueue/dequeue pointers too" 2020-06-18 18:45:15 -07:00
qctecmdr
b0380a354f Merge "power: supply: qti_battery_charger: support wireless firmware update" 2020-06-18 18:45:15 -07:00
qctecmdr
0a28c83f4e Merge "defconfig: Add support for compiling sdxlemur target" 2020-06-18 18:45:15 -07:00
qctecmdr
2f2ac06609 Merge "USB: f_accessory: Set manufacturer and model string to default value" 2020-06-18 18:45:14 -07:00
qctecmdr
eaba670acb Merge "mmc: sdhci-msm: Ensure SD card power isn't ON when card removed" 2020-06-18 18:45:14 -07:00
qctecmdr
4bc6723b0c Merge "net: qrtr: haven: Read peer name from device tree" 2020-06-18 15:30:54 -07:00
qctecmdr
4f34190efb Merge "driver: pinctrl: Add reserved GPIOs for Shima" 2020-06-18 10:42:14 -07:00
qctecmdr
bac8eddf4a Merge "defconfig: arm64: Enable SDPM clock monitor for Lahaina" 2020-06-18 10:42:14 -07:00
qctecmdr
0a1e159645 Merge "defconfig: lahaina: Enable LIMIT_MOVABLE_ZONE_ALLOC" 2020-06-18 10:42:14 -07:00
qctecmdr
a91e5519be Merge "usb: dwc3: gadget: Remove unnecessary checks" 2020-06-18 10:42:13 -07:00
qctecmdr
b84282aee9 Merge "mm: process_reclaim: consider compound pages" 2020-06-18 07:41:45 -07:00
qctecmdr
9d579d774a Merge "pinctrl: qcom: Update configuration for Shima" 2020-06-18 07:41:44 -07:00
Mukesh Ojha
5a08ead3da driver: pinctrl: Add reserved GPIOs for Shima
Certain GPIOs are reserved for secure world and cannot be accessed by HLOS.
Supply "reserved_gpios" to msm_pinctrl to mark these pins as invalid.

Change-Id: Ic8f45181b2210a6295bba1bdec45d24e607bede9
Signed-off-by: Mukesh Ojha <mojha@codeaurora.org>
2020-06-18 05:10:51 -07:00
qctecmdr
6447752153 Merge "ANDROID: scsi: ufs: Handle clocks when lrbp fails" 2020-06-18 04:30:10 -07:00
qctecmdr
8e37ccbf8f Merge "soc: qcom: crypto-qti-hwkm: Return negative errors" 2020-06-18 04:30:10 -07:00
qctecmdr
b94374d1be Merge "scsi: ufshcd-crypto-qti.c: do not resume for key reprogram" 2020-06-18 04:30:10 -07:00
qctecmdr
caa193790c Merge "aarch64: ABI: Update snapshot with newer libabigail version" 2020-06-18 04:30:09 -07:00
qctecmdr
983251f46b Merge "drivers: qcom: rpmh: caching batch requests should flag the cache dirty" 2020-06-18 04:30:09 -07:00
qctecmdr
e039aac6bb Merge "msm: kgsl: Add support for gpu busy multiplier" 2020-06-18 04:30:09 -07:00
qctecmdr
317ee8f0c6 Merge "arm64: defconfig: Add support for KPROBE for lahaina/shima/holi debug" 2020-06-18 04:30:08 -07:00
Prakash Gupta
9d12d29a2d taskstats: remove redundant MM_STAT config check
Userspace does not have access to MM_STAT configs, so remove redundant
config checks.

Change-Id: I0ec0807a1e62bd5932f01ed285f2175f27900e37
Signed-off-by: Prakash Gupta <guptap@codeaurora.org>
2020-06-18 16:39:12 +05:30
Mukesh Ojha
39b9853678 pinctrl: qcom: Update configuration for Shima
Update pinctrl configuration for Shima, to match the
latest released configuration.

Change-Id: I1537735755e1a0384a9c48dca6184a85b49b2237
Signed-off-by: Mukesh Ojha <mojha@codeaurora.org>
2020-06-18 01:35:39 -07:00
Manu Gautam
5be8f883fc mhi: core: add mhi_device_get_sync_atomic() to wait until M0
There is a possibility of client driver's dev_wake request
as part mhi_device_get() racing with M1 state transition
event processing. This can result in a scenario where client
finds MHI state as M0 after mhi_device_get() returns only to
be changed later as M1 event processing is still pending on
different CPU core.
It causes M0 -> M2 -> M0 state transition after mhi_device_get()
has already returned. This isn't expected by client and currently
treats that as fatal error. Also, as per MHI spec host must allow
M1 -> M2 transition for device and it shouldn't abort that.

However, clients can ignore that transition as device is expected
to immediately move from M2 to M0 without entering deep sleep
state. Hence, it must be safe to access their MMIO.
To simplify this logic, introduce mhi_device_get_sync_atomic()
function that can be used by clients to achieve the same and once
it returns success they don't need to have any explicit MHI state
checks.

Change-Id: I0b4a1ad723a0444ee2402bf171fc5ffc46afcdce
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
2020-06-17 23:24:02 -07:00
qctecmdr
590814e336 Merge "scripts: headers_install: Turn CONFIG_* leak checker to report error" 2020-06-17 16:48:21 -07:00
qctecmdr
60c5922a88 Merge "defconfig: Add UAPI_HEADER_TEST for Lahaina GKI" 2020-06-17 16:48:21 -07:00
Lina Iyer
ac290b4993 drivers: qcom: rpmh: caching batch requests should flag the cache dirty
The sleep/wake state batch requests are saved in a linked list and
flushed along with other sleep/wake request when entering system low
power modes. Caches are flushed only if the state flag is marked dirty.

A race situation could cause the batch sleep/wake requests to not be
flushed. Here is how this could happen -

- Interconnect driver (ICC) invalidates the sleep/wake requests
	- RSC driver clears the TCSes (BCM, VRM, ARC sleep votes cleared)

- ICC sends an active state response-required request
	- RSC driver sends the AMC request
	- RPMH waits on the response, calls wait_for_completion

- Scheduler schedules idle thread
	- cpuidle enters cluster idle state
		- RPMH flushes cache and marks cache clean
		 (no BCM votes in TCS)

- RSC driver receives IRQ response
	- RPMH calls complete()

- ICC worker thread resumes execution
	- ICC driver calls RPMH driver with updated sleep and wake votes
		- RPMH caches the request, *cache is NOT marked dirty*

- Scheduler schedules idle thread
	- cpuidle enters cluster idle state
		- Cache is clean and nothing to flush
	- CPU enters idle
		=>ICC sleep/wake votes are not sent

Fix this by dirtying the cache state even when caching batch requests.

Change-Id: I7613e665d181f8abb27915d622442e7b981f9fcc
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
2020-06-17 15:24:50 -06:00
qctecmdr
5df03724c4 Merge "scsi: ufs: Dump PA_VS_STATUS_REG1 in eh" 2020-06-17 08:24:01 -07:00
qctecmdr
f50a6e676b Merge "msm: adsprpc: Fix array index underflow problem" 2020-06-17 08:24:00 -07:00
qctecmdr
8e2fab80f7 Merge "soc: qcom: spcom: remove excessive debug prints" 2020-06-17 08:24:00 -07:00
qctecmdr
354981abde Merge "sched/walt: Fix negative count of sched_asym_cpucapacity static key" 2020-06-17 08:24:00 -07:00
qctecmdr
be77d9f54e Merge "tmc-etr: Correct condition for SW USB mode when setup sysfs buf" 2020-06-17 02:00:28 -07:00
qctecmdr
58bcf322e6 Merge "soc: qcom: mem-buf: Treat zero-sized sg-lists as invalid inputs" 2020-06-17 02:00:28 -07:00
qctecmdr
9374a3bfd2 Merge "mm: introduce CONFIG_SPECULATIVE_PAGE_FAULT" 2020-06-17 02:00:28 -07:00
qctecmdr
2791c02ab1 Merge "cpufreq: qcom: Add code to support module removal" 2020-06-17 02:00:27 -07:00