Commit graph

879,847 commits

Author SHA1 Message Date
Jagadeesh Kona
b7d2a71622 clk: qcom: gcc-shima: Add support for GCC clock driver
Add support for global clock controller for peripheral clock
clients to be able to request for the clocks.

Change-Id: I528821a299fee139d23947bc8caa5674ddef9687
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
2020-04-17 04:35:07 -07:00
Jagadeesh Kona
c948dc3cd1 dt-bindings: clock: Update clock IDs and BCRs of GCC for SHIMA
Update the clock IDs and BCRs of Global Clock Controller for SHIMA.

Change-Id: Iec2722e6edc1d454a29d084062b8356af08b17b7
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
2020-04-15 10:27:54 +05:30
Jagadeesh Kona
a08051bcb6 dt-bindings: clock: Update clock ids of GCC for SHIMA
Add clock id for GCC PCIE throttle core clock and remove clock ids of few
dummy clocks on SHIMA.

Change-Id: I71d41fc078c1b9d9d89dbc6b44e1296fe6b3c9ed
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
2020-04-13 16:11:02 +05:30
qctecmdr
521e5186f1 Merge "sched/fair: Improve the scheduler" 2020-04-12 19:05:43 -07:00
qctecmdr
dd98d97d8d Merge "soc: qcom: rpmh_master_stat: Add island stats support" 2020-04-12 19:05:43 -07:00
qctecmdr
e815c948a3 Merge "defconfig: arm64:Enable CDSPRM driver for Lahaina" 2020-04-12 08:11:30 -07:00
Bavyasritha Alahari
7ddfe69e25 defconfig: arm64:Enable CDSPRM driver for Lahaina
CDSPRM module implements a RPMSG interface to communicate with CDSP
while providing a way for CDSP to vote for CPU L3 clock, CPU QoS to
benefit CDSP applications performance.

Change-Id: I46c6407a6f4d531f3a9ec84d5ec4e506db5ca120
Acked-by: Sreekanth Gande <sgande@qti.qualcomm.com>
Signed-off-by: Bavyasritha Alahari <alahari@codeaurora.org>
2020-04-12 11:04:14 +05:30
qctecmdr
06e5250832 Merge "scsi: ufs-qcom: dump phy registers on error" 2020-04-11 21:33:11 -07:00
qctecmdr
6726b022eb Merge "Bluetooth: Add support to get chipset version from device tree" 2020-04-11 21:33:10 -07:00
qctecmdr
f68e833a32 Merge "usb: xhci: Increase xhci halt timeout" 2020-04-11 21:33:10 -07:00
qctecmdr
5a69e5bb3e Merge "interconnect: qcom: Fix the commit bit not getting set" 2020-04-11 21:33:10 -07:00
qctecmdr
a0cf010626 Merge "msm: adsprpc: register wake-source clients during driver init" 2020-04-11 21:33:09 -07:00
qctecmdr
447a5ff2c1 Merge "defconfig: lahaina: Disable qbt_handler from QGKI config" 2020-04-11 21:33:09 -07:00
qctecmdr
c96bbdd153 Merge "arm64: defconfig: Enable boot_stats driver for Lahaina" 2020-04-11 21:33:09 -07:00
qctecmdr
6c32e17330 Merge "drivers: soc: qti: Fix data type for uapi header" 2020-04-11 21:33:09 -07:00
qctecmdr
f4913de490 Merge "msm: kgsl: Check the return value of regulator_enable" 2020-04-11 21:33:08 -07:00
qctecmdr
5490b09d03 Merge "dt-bindings: clk: Remove unused cpuss clocks for Lahaina" 2020-04-11 21:33:08 -07:00
qctecmdr
d7c669fea5 Merge "net: qrtr: Check for exisiting waiters" 2020-04-11 21:14:46 -07:00
qctecmdr
916331668a Merge "cnss2: Check driver link state before prevent/allow PCIe L1" 2020-04-11 21:14:46 -07:00
qctecmdr
21aa3d3230 Merge "iommu/arm-smmu: Add support to disable page-table coherency" 2020-04-11 21:14:46 -07:00
qctecmdr
886c117ec6 Merge "msm: ipa4: flow control changes for rmnet pipe" 2020-04-11 21:14:45 -07:00
qctecmdr
6c1dddc89d Merge "usb: gadget: qdss: Add NULL check against priv_usb with usb_qdss_close()" 2020-04-11 21:14:45 -07:00
qctecmdr
53486a4848 Merge "drivers: of-thermal: Handle krealloc failure correctly" 2020-04-11 21:14:45 -07:00
qctecmdr
f04392300d Merge "arm64: defconfig: define ARCH_LAHAINA for VM image to compile" 2020-04-11 21:14:45 -07:00
qctecmdr
34ce354498 Merge "msm: pcie: update suppressible clock info" 2020-04-11 21:14:44 -07:00
qctecmdr
6e0b43924a Merge "ANDROID: selinux: modify RTM_GETLINK permission" 2020-04-11 21:14:44 -07:00
qctecmdr
c22737e769 Merge "firmware: qcom_scm: Fix the __qcom_scm_is_call_available" 2020-04-11 21:14:43 -07:00
qctecmdr
a4fa30e6a6 Merge "msm: pcie: add PCIe GDSC disable/enable for DRV suspend/resume" 2020-04-11 21:14:43 -07:00
qctecmdr
43d3a8b012 Merge "msm: cvp: add cache operation control flag" 2020-04-11 13:28:34 -07:00
qctecmdr
e3355ff92a Merge "cnss2: Handle race between register driver and reboot properly" 2020-04-11 13:28:34 -07:00
qctecmdr
44abeafb57 Merge "soc: qcom: pmic_glink: Verify the message length" 2020-04-11 13:28:34 -07:00
qctecmdr
61ade967b7 Merge "power: supply: qti-battery-charger: Handle incorrect thermal levels" 2020-04-11 13:28:33 -07:00
qctecmdr
e814c38deb Merge "mm: correct ALLOC_WMARK_MIN flag check for atomic allocations" 2020-04-11 13:28:33 -07:00
qctecmdr
8be639b1d4 Merge "mm: reap tasks only killed by low memory killer" 2020-04-11 13:28:33 -07:00
qctecmdr
000cfc1ef2 Merge "power: supply: qti_battery_charger: add support to set fake SOC for battery" 2020-04-11 13:28:33 -07:00
qctecmdr
2087769c27 Merge "interconnect: qcom: Fix BW requests to L3_SHARED returning -EINVAL" 2020-04-11 13:28:32 -07:00
qctecmdr
ee26b2fc8a Merge "soc: qcom: add CDSP request manager" 2020-04-11 13:28:32 -07:00
qctecmdr
eef803ab52 Merge "msm: cvp: Avoid releasing buffers during boot" 2020-04-11 13:28:32 -07:00
Chris Lew
cdb150a515 net: qrtr: Check for exisiting waiters
Some non-blocking clients may not wait for the OUT event from select or
poll before resending to a flow controlled port. Check for exisiting
waiters before allocating a new one so these clients do not exhaust the
memory pool.

Change-Id: I5fc40d5b1d1819ea5bf94438c04ee42b42639ebc
Signed-off-by: Chris Lew <clew@codeaurora.org>
2020-04-10 17:58:55 -07:00
qctecmdr
31ef58ab90 Merge "haven: add stubs to haven client exposed APIs" 2020-04-10 15:56:33 -07:00
Satish kumar sugasi
79610859b3 Bluetooth: Add support to get chipset version from device tree
parse compatible flag from BT Device tree to get Bluetooth
chipset version and send to userspace via ioctl call.

Change-Id: Iddcae25df2e854a55a745bc127277552a799e3e4
Signed-off-by: Satish kumar sugasi <ssugas@codeaurora.org>
2020-04-10 12:13:32 -07:00
Bavyasritha Alahari
07b0a87f34 soc: qcom: add CDSP request manager
CDSPRM module implements a RPMSG interface to communicate with CDSP
while providing a way for CDSP to vote for CPU L3 clock, CPU QoS to
benefit CDSP applications performance. The module also implements
an interface with NPU for Cx i-peak limit management and registers
cooling devices for CDSP and HVX thermal mitigation.

Change-Id: I5aa592cb8de19367f7361e1f31d1077ceba386df
Acked-by: Sreekanth Gande <sgande@qti.qualcomm.com>
Signed-off-by: Bavyasritha Alahari <alahari@codeaurora.org>
2020-04-09 22:16:58 -07:00
Subbaraman Narayanamurthy
2a9286f089 power: supply: qti_battery_charger: add support to set fake SOC for battery
Setting a fake battery SOC (state of charge) is useful to test
different mitigation levels. Add support for it by exposing
fake_soc under qcom-battery class which can be set only when
CONFIG_QTI_PMIC_GLINK_CLIENT_DEBUG is enabled.

To set fake_soc of 50%,

 echo 50 > /sys/class/qcom-battery/fake_soc

To clear fake_soc so that actual battery SOC can be displayed,
any value other than 0-100 can be set to fake_soc.

 echo -1 > /sys/class/qcom-battery/fake_soc

Change-Id: Ibff337fb4da9d4e9aadbe148f3eecca9e2d69604
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
2020-04-09 17:10:48 -07:00
Subbaraman Narayanamurthy
a91100b971 soc: qcom: pmic_glink: Verify the message length
Currently, data received from the remote subsystem is delivered
to the clients as-is if they've registered for receiving it. This
can cause unintended extraneous buffer reads if the length of the
received message is too small. Verify that the message length is
at least the PMIC Glink header size.

Change-Id: I3774d9d5331794c509bda89f40f4ead2e0ed3843
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
2020-04-09 15:26:20 -07:00
Murali Nalajala
32637a594d haven: add stubs to haven client exposed APIs
There are Non-VM (Virtual Machine) supported target drivers which
may refer some of the APIs defined for VMs. But those drivers are
compiled irrespective of VM or non-VM configurations. Add stubs to
support to compile drivers for non vm supported targets.

Change-Id: Ibc0c2c55b3b264c43c4793f153e723f8d344423a
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
2020-04-09 14:22:12 -07:00
Yue Ma
688818c547 cnss2: Handle race between register driver and reboot properly
Register driver should be skipped if reboot is already in progress.
Also firmware boot timer should be stopped if register driver work
has been scheduled but gets killed later to avoid timing out because
of the reboot.

Change-Id: Iae4de860329a82416bfa58967095a4de7b509813
Signed-off-by: Yue Ma <yuem@codeaurora.org>
2020-04-09 12:00:20 -07:00
Elliot Berman
21a9eb8e4b haven: rm: Remove pr_err on get_vmid
If RM is not set up, drivers such as ion may be frequently calling
hh_rm_get_vmid and causing a console message that a VMID could not be
found. Drivers should be correctly handling the error case, so remove
the pr_err here to not fill console messages.

Change-Id: I2026d9481b6d58a89fb2f546bf76b29566e5f3d7
Signed-off-by: Elliot Berman <eberman@codeaurora.org>
2020-04-09 11:55:20 -07:00
Elliot Berman
18175354e0 haven: rm: Add haven vIRQ lending library
Add library for client drivers to lend interrupts to each other.

Change-Id: I4c60e0443d178e83c0bb4ec824915e4bdadb9c39
Signed-off-by: Elliot Berman <eberman@codeaurora.org>
2020-04-09 11:55:19 -07:00
Elliot Berman
479830ad51 haven: rm: Add calls to relase/reclaim IRQs
A VM may release a lent IRQ back to its lender. The lendee VM notifies
the resource manager that it may give the interrupt back to the lender
via its interrupt handle. The lender then must notify the lender VM that
it has released the interrupt. The lender VM must then reclaim the
interrupt via the handle.

Change-Id: Ic76f5a3692b4041bc3f260b4add06da11746f19e
Signed-off-by: Elliot Berman <eberman@codeaurora.org>
2020-04-09 11:55:19 -07:00
Elliot Berman
068a9a830d haven: rm: Allow IRQ lender to learn about the IRQ handle
An IRQ lender driver will likely ought to need to use the IRQ handle to
reclaim the interrupt when the lendee is done with the interrupt.

Change-Id: I0b791ecfb7b169d5cf2677d324e9aceea51feb5d
Signed-off-by: Elliot Berman <eberman@codeaurora.org>
2020-04-09 11:55:18 -07:00