Commit graph

2,112 commits

Author SHA1 Message Date
Jayasri Sampath Kumaran
bd90eaaa4b disp: msm: sde: fix kms NULL pointer access in encoder IRQ control
A possible kms NULL pointer access is found during CPU vote for IRQ
when kms isn't NULL checked before accessing structure members. So,
perform kms NULL check before accessing members.

Change-Id: I137759ea0723be8580e9166c983d1ba38f4eb281
Signed-off-by: Jayasri Sampath Kumaran <quic_jsampath@quicinc.com>
2025-02-03 22:09:53 -08:00
Jinfeng Gu
0289b7a3f7 disp: msm: dsi: add null pointer check in dsi_display_dev_remove
This change add display null pointer check in dsi_display_dev_remove.

Change-Id: Ib31756c3b22256d19cbcb508f60de4550e3834e1
Signed-off-by: Jinfeng Gu <quic_gjinfeng@quicinc.com>
2024-09-24 11:58:00 +05:30
Akash Gajjar
9d53b47d4e disp: msm: sde: program read pointer after configuring vsync_counter_en
Program the read pointer after configuring the tearcheck registers.
The read pointer register should be configured after VSYNC_COUNTER_EN
is set as per hw programming sequence.

Change-Id: I2fa1429798fab51d08091e74a33f1b1c4382eafe
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
(cherry picked from commit fce2fc595f1a9881255faa651e8d1b9e43cbf906)
2024-02-12 01:22:31 -08:00
Sai Srujana Oruganti
2653c8e813 disp: msm: add support for hibernation
Enable support for hibernation config.

Change-Id: Ib0e2ca6ac57aec566171b2f72e2b6822e2d9fde2
Signed-off-by: Sai Srujana Oruganti <quic_osaisruj@quicinc.com>
2023-11-29 14:03:05 +05:30
Jayaprakash Madisetty
74e59e97a7 disp: msm: sde: skip msm_lastclose if display is stuck in splash
This change skips msm_lastclose, when splash enabled builtin-displays
equals number of actual displays and are stuck in continuous splash.
It fixes the issue seen with change commit id 548b17185e95
("disp: msm: send power_on event in dual display composer kill scenario").

Change-Id: I1f5417d8945db621dc20ab0a9cc0146eabae5e22
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
2023-10-09 04:15:55 -07:00
Jayaprakash Madisetty
38a180a911 disp: msm: cancel all delayed_works before triggering msm_lastclose
This patch cancels all the delayed_off_works if scheduled and flushes
the display threads for completion during msm_lastclose. The commit
from msm_lastclose client modeset to disable any crtcs if enabled
is always scheduled on primary crtc_commit thread. In the current issue,
delayed_off_work is scheduled on secondary display crtc_commit thread
and primary crtc_commit thread is scheduled to turn off active crtcs
from msm_lastclose leading to null dereference access of sde_enc's
cur_master. This race is avoided by serializing the operations in
msm_lastclose.

Change-Id: I30cc95b925c8134f0064816ebe2cfdb86a49fb36
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
2023-10-09 04:15:43 -07:00
Steve Cohen
9c77f40c14 disp: msm: sde: cancel delayed work items during TUI transition
Delayed work items may touch HW registers. If these work items
run while HW is not owned by this VM it will lead to invalid
access. This happens in video mode as HAL does not disable idle
power-collapse in this mode. It can also happen with ESD status
if lastclose or TUI transition failure occurs.

Although there is a contract with user mode to turn off certain
features, kernel cannot rely on it to always do the right thing.
Prevent potential crashes from certain corner cases by cancelling
all delayed work items when the HW ownership is transferred.

Change-Id: I08da17f2ce72bf2fddf71924c3e8edd2e2715be8
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2023-10-09 04:15:01 -07:00
Jayaprakash Madisetty
581199cba2 disp: msm: send power_on event in dual display composer kill scenario
On composer kill event, drm lastclose occurs during which suspend
commit gets triggered on primary. If secondary display is stuck in
continuous splash, then we do a early return without triggering this
suspend commit. On composer start, userspace waits for power on
event, but the drm_driver has never entered suspend state, so power
on event is never sent to userspace. This causes HWC deadlock side
effect and the current change triggers null_commit on secondary
display and then issues a suspend commit on both the displays to
avoid this deadlock issue.

Change-Id: I126f43ba3dd2c3bfa83346e8fd4678f35527893d
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
2023-10-03 01:52:02 -07:00
qctecmdr
7c41afb5ec Merge "disp: msm: sde: cancel delayed idle_notify_work beginning of every commit" 2023-02-09 18:33:32 -08:00
Jayaprakash Madisetty
a4fdef4c12 disp: msm: sde: drop suspend state if commit is skipped
Drop refcount on pm_suspend commit state if atomic
commit is skipped due to failure. It will avoid frame
trigger during pm_resume call.

Change-Id: Iecd98b106454c82c81a1ef9faaf1af4be2bf19e6
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
2023-01-23 22:58:05 +05:30
Mahadevan
0a00bff777 disp: msm: sde: cancel delayed idle_notify_work beginning of every commit
In some cases HAL sets CRTC_PROP_IDLE_TIMEOUT property to zero
and idle_notify_work which is already scheduled will send notfication
on timer expire. This will cause janks in subsequent commit. This
change cancels the existing delayed idle_notify work and will get
rescheduled after frame trigger if CRTC_PROP_IDLE_TIMEOUT property is
non zero.

Change-Id: I8b9ebce8282425f55838b94cfd345b5e733fa645
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
2023-01-16 15:39:28 +05:30
Rajeev Nandan
90a2dca98f disp: msm: dsi: add missing dsi ctrl mutex lock in host timing update
Acquire dsi_ctrl->ctrl_lock lock before programming dsi ctrl
registers. Failing this may lead to race conditions in register
programming.
Add missing mutex lock inside dsi_ctrl_host_timing_update().

Change-Id: Ic86cbe282333c0b4d63ae3d5b3356a5d24752203
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
2022-11-22 23:37:50 -08:00
qctecmdr
73a4620464 Merge "disp: msm: dsi: Handle absence of dsi select clocks in device-tree" 2022-11-15 01:55:43 -08:00
Mahadevan
d538367ebd disp: rsc: update mode-1 threshold config to 1 hz
Update mode-1 threshold configuration to 1 hz to avoid
selecting mode-2 if panel vsync is irregular.

Change-Id: I9d48d088ac1e84f9d0e422d006458527e1944ed8
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
2022-10-26 15:50:44 +05:30
Srihitha Tangudu
1d01b6c5e1 disp: msm: dsi: Handle absence of dsi select clocks in device-tree
Initialize pll clocks to NULL and warn if dsi select clocks are not
defined in device-tree.

Change-Id: If831692021278b020d49c06c3bb15d631c0376a4
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
2022-10-21 16:13:33 +05:30
Linux Build Service Account
c714fc0871 Merge "disp: msm: dsi: clear the panel esd_recovery_pending in power on commit" into display-kernel.lnx.5.4 2022-10-11 10:27:02 -07:00
Srihitha Tangudu
31a6cf6c8b disp: msm: dsi: clear the panel esd_recovery_pending in power on commit
Currently the panel esd_recovery_pending flag is cleared for every mode
set. The ESD recovery completes only after the suspend and resume. Clear
the flag only during power on commit.

Change-Id: I97e370feba0aad34558e4675168b4bcb7f5901ca
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
2022-10-05 23:22:18 -07:00
Soutrik Mukhopadhyay
25edb2950d drm: msm: remove YUV format setting
Remove the YUV format setting, will use the upstream code
for YUV mode check.

Change-Id: I24f059ff7cd4cf64f41d7f77bfa6517df0cccfde
Signed-off-by: Zhao, Yuan <yzhao@codeaurora.org>
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
2022-10-06 10:35:59 +05:30
Mahadevan
d5dd61b011 disp: msm: sde: fix min ib vote in mnoc and ebi_ib path
This change sets proper minimum vote for lcc_mnoc and
ebi_ib path.

Change-Id: Idbb8667a7416e359e848d3f4dc266531979639d3
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
2022-09-20 20:54:09 +05:30
Deven Solanki
40e19ff3ed disp: msm: dsi: add support for dsi config
Add uio support for dsi config.

Change-Id: I2098a6b3abe95794cf3e08dbb34198543d15385c
Signed-off-by: Deven Solanki <quic_dsolanki@quicinc.com>
2022-08-18 00:16:34 -07:00
qctecmdr
71b489f33e Merge "disp: msm: add msm framebuffer emulation" 2022-08-16 21:17:12 -07:00
Kai Xing
7015ffdd0b disp: msm: add msm framebuffer emulation
This change copies msm_fbdev.c from msm-5.14 kernel, which adds
frame buffer support to display driver. And this file is from
msm-5.4 commit <5fce077d> ("drm: msm: Fix the format prints in
display driver").

Change-Id: I113cb6441334ff6b61cfd15cf863c325d51091b4
Signed-off-by: Kai Xing <quic_kxing@quicinc.com>
2022-08-03 15:06:14 +05:30
Kai Xing
29a7eac491 makefile: add gki config support for display techpack for kona
Add required changes to makefile and enable the gki
config keys for kona target compilation.

Change-Id: I39422750ac6000078278ddc7705e7148f6b0ae6b
Signed-off-by: Kai Xing <quic_kxing@quicinc.com>
2022-08-01 14:04:31 +05:30
Naresh Kumar Lingagalla
ed8c317940 Revert "disp: msm: dsi: Add DSI PLL support for 7nm_v4_1 arch"
This reverts commit a965033fba.

Change-Id: Ifb3d9b1a10a28cd281459174a9291fea79ec781d
Signed-off-by: Naresh Kumar Lingagalla <quic_nlingaga@quicinc.com>
2022-07-07 10:11:43 +05:30
Kai Xing
a965033fba disp: msm: dsi: Add DSI PLL support for 7nm_v4_1 arch
Add DSI PLL support for 7nm_v4_1 architecture

Change-Id: I4adf1ec6ed40fea16aa80579d34a3c918faa8478
Signed-off-by: Kai Xing <quic_kxing@quicinc.com>
2022-06-14 21:46:34 +05:30
Sai Srujana Oruganti
6a0f0b0f1f disp: msm: sde: disable dsi ctrl regulator during deepsleep
Disable DSI ctrl regulator while entering deepsleep and restore
during resume. Refactor deepsleep related code to helper function.

Change-Id: If6da0471db59fbdfa9d9855ee1464fcab90cae15
Signed-off-by: Venkata Prahlad Valluru <quic_vvalluru@quicinc.com>
Signed-off-by: Sai Srujana Oruganti <quic_osaisruj@quicinc.com>
2022-05-30 22:17:15 -07:00
qctecmdr
5cf1bae57a Merge "disp: msm: sde: update uidle ctl register only for master encoder" 2022-05-24 07:14:15 -07:00
Yashwanth
5e4c130f36 disp: msm: sde: update uidle ctl register only for master encoder
In case of dual dsi usecase, since both the encoders use
the same CTL path, this change ensures that uidle ctl
settings are updated only by the master encoder.

Change-Id: I7bd75ae0195d34f0c1810403fa5e390fbaa64ed0
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
2022-05-16 11:52:13 +05:30
qctecmdr
be3f2e68c9 Merge "disp: msm: add skip panel power off dt property" 2022-05-08 06:57:24 -07:00
Jayaprakash Madisetty
09ec818831 disp: msm: avoid minidump region addition for mdss register dumps
This change enables minidump for register dumps, debug bus collection
based on CONFIG_QCOM_VA_MINIDUMP config. The minidump driver in 5.4 kernel
needs physical contiguous memory allocation as a requirement. The
minidump collection failure is seen with commit fdf36d7124
("disp: msm: use vzalloc for large allocations") and it uses
vzalloc to address memory allocation failure with order 5. This
patch will disable minidump collection for regdumps, debug bus
to address minidump collection failure.

Change-Id: If5ff91ff95279ee2997765599dbeab16ac2dae60
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
2022-05-04 12:31:28 +05:30
Sai Srujana Oruganti
fc3be600f7 disp: msm: add skip panel power off dt property
This property skips the panel power off for panels
with in-cell design.

Change-Id: I61ff7b8696940b74a58c79eef5b9cd43fd551c01
Signed-off-by: Sai Srujana Oruganti <quic_osaisruj@quicinc.com>
2022-04-28 10:58:11 -07:00
qctecmdr
0bd399fda0 Merge "disp: msm: dsi: handle read cmd tx failure from dsi host transfer" 2022-04-27 23:10:05 -07:00
Sai Srujana Oruganti
2b84165300 disp: msm: dsi: avoid setting ulp load to disable load
When there is no ulp load entry, ulp load should be set to
enable load.

Change-Id: I531108b4d2137cf9262874bc411ff06592302374
Signed-off-by: Sai Srujana Oruganti <quic_osaisruj@quicinc.com>
2022-04-18 15:38:49 +05:30
qctecmdr
a2aacd57a3 Merge "disp: msm: sde: unset and set clk parents during pm_suspend" 2022-04-17 05:31:50 -07:00
Srihitha Tangudu
43cb27c187 disp: msm: dsi: handle read cmd tx failure from dsi host transfer
Currently we are handling only write command transfer failures from
dsi host transfer path. Modify check to handle read command transfer
failures.

Change-Id: Iee1dbf46a4374819e6d6425eb5acece8ec1fb8b1
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
2022-04-14 01:20:23 -07:00
qctecmdr
bb3029af82 Merge "disp: msm: dsi: handle panel detection after a pp done timeout" 2022-04-13 21:40:08 -07:00
Venkata Prahlad Valluru
9a6ed8620e disp: msm: sde: unset and set clk parents during pm_suspend
Currently link clk parent set/unset are done as part of dsi_prepare
and dsi_unprepare, but in case of deepsleep with display ON, these
will not be called. Due to mismatch in parent between clk
framework and actual parent, subsequent clk_set_parent will
early return without setting the parent.

To avoid this condition, do set parent to xo, as part of
pm_suspend and restore to link clk source in pm_resume.

Change-Id: I626899304580f9d9fbcc92cd8b139cd89cd48999
Signed-off-by: Venkata Prahlad Valluru <quic_vvalluru@quicinc.com>
2022-04-14 02:28:16 +05:30
qctecmdr
1438587222 Merge "disp: msm: dsi: Fix DMA window scheduling programming" 2022-04-11 20:39:05 -07:00
Kashish Jain
9e5185ad69 disp: msm: dsi: handle panel detection after a pp done timeout
It has been observed that TE check may fail even if status read
is passing. Panel detection should be successful only if both
TE check and register read (if supported) pass.

Change-Id: I8d2c5d4139561fe533fc148124b7dde54b63c24e
Signed-off-by: Kashish Jain <quic_kashjain@quicinc.com>
2022-04-05 12:20:50 +05:30
Jayaprakash Madisetty
fdf36d7124 disp: msm: use vzalloc for large allocations
Large allocations using kzalloc can lead to timeouts. This updates
the allocation calls accordingly to use vzalloc to remove
requirements on contiguous memory.

Change-Id: Ica54483787509ed0e9283289fc9d523e8cde9238
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
2022-03-31 14:48:52 +05:30
qctecmdr
a67699f42b Merge "disp: msm: sde: Fix data width calculation when widebus is enabled" 2022-03-24 23:59:45 -07:00
qctecmdr
a3d1758f89 Merge "drm: msm: call rsc hw_init after hibernation" 2022-03-23 11:33:22 -07:00
Kashish Jain
ebd2c679df disp: msm: sde: Fix data width calculation when widebus is enabled
Adjust the data width calculation to reduce the rounding off error
when the widebus is enabled.

Change-Id: Ia2fa4536ce519548989e2befcb22fb685f286c9e
Signed-off-by: Kashish Jain <quic_kashjain@quicinc.com>
2022-03-22 16:11:16 +05:30
Sai Srujana Oruganti
f9b6363fb7 drm: msm: call rsc hw_init after hibernation
When device boots from hibernation, probe function is not called
and rsc need to initialize the hw at the first client update call.

Change-Id: Iba3a3aaebbb8052ce93b8aac1746f33ea80795fb
Signed-off-by: Sai Srujana Oruganti <quic_osaisruj@quicinc.com>
2022-03-21 23:28:21 +05:30
Samantha Tran
3823e9f6ed disp: msm: sde: remove redundant backlight update
Current logic will unnecessarily call backlight update
twice in cases where backlight level is changing. When
this happens, there is a potential delay waiting for the
first command to complete before sending the second
backlight update with the same value. This change removes
one backlight call and now only calls update if the
property is marked as dirty.

Change-Id: I260f0d73b3a5af9ced7ae261d247595f965a8d9e
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2022-03-20 23:42:18 -07:00
Rajeev Nandan
a63678a172 disp: msm: dsi: Fix DMA window scheduling programming
In DMA start window scheduling, TRIG_CTRL.COMMAND_MODE_DMA_TRIGGER_SEL
is programmed to SW + DMA start window trigger. But if DMS switch
comes after command is scheduled, COMMAND_MODE_DMA_TRIGGER_SEL gets
reprogrammed to SW trigger leading to command transfer failure.

Program the COMMAND_MODE_DMA_TRIGGER_SEL only from the CMD DMA Tx path.

Change-Id: I01062497bb70aa5fdcb25be3715c7cbc4c68b681
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
2022-03-17 12:14:26 +05:30
qctecmdr
0777752947 Merge "disp: msm: sde: take min ib votes from perf config" 2022-03-09 18:49:35 -08:00
Andhavarapu Karthik
caa5fa4247 disp: msm: sde: take min ib votes from perf config
Changes are made to get minimum ib vote for each bus from
device tree entries rather than static values.

Change-Id: Ibecb44ac6b8673c5d5b8979014c215ab3ce9e43f
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
2022-03-04 13:26:40 +05:30
Jayaprakash Madisetty
3c0f029ebb disp: msm: sde: validate plane mode and gem obj flags
Add changes to validate the plane fb_translation mode
and dma_buf flags of drm_gem_obj attached to plane. It
avoids device panic on S2 translation fault and fails the
drm_atomic_commit for which mismatch is detected. In
current codeflow, only S1 mappings are modified when dma_buf
is detached from Non_sec CB and attached to secure SB as part
of msm_gem_get_iova_locked API, but S2 mapping entries are
not modified and this crash is seen.

Change-Id: I6bced92994cd8681cf69231e41bec0c262dafd33
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
2022-02-28 16:08:52 +05:30
Rajeev Nandan
1f5cc03a33 disp: msm: dsi: fix compressed RGB101010 support
The destination format for compressed rgb101010 should be
the same as rgb888. After adding uncompressed RGB101010 support,
the programming for compressed rgb101010 went wrong.
Fix this to re-enable compressed rgb101010 format support.

Change-Id: I805e15df14dda8ff0653a0dba8c4efe3fe0681fd
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
2022-02-22 22:50:10 +05:30