Commit graph

891,754 commits

Author SHA1 Message Date
Sriharsha Allenki
c4e5ee5be1 usb: typec: Fix setting of invalid value of opmode
Setting opmode to invalid values would lead to a
paging fault failure when there is an access to the
power_operation_mode.

Prevent this by checking the validity of the value
that the opmode is being set.

Change-Id: I9863df1e84a947fb04e29d214c1dec61ccc5ee72
Signed-off-by: Sriharsha Allenki <sallenki@codeaurora.org>
2020-10-21 11:38:59 +05:30
qctecmdr
986ca5b1f1 Merge "msm: kgsl: Skip SP_INST_TAG and SP_INST_DATA dump in snapshot for A6xx" 2020-10-20 09:24:14 -07:00
qctecmdr
dfcf991962 Merge "msm: kgsl: Cleanup kgsl_iommu_probe properly on error" 2020-10-20 09:24:14 -07:00
qctecmdr
1d7dde2504 Merge "msm: kgsl: Clear ddr_table pointer after free" 2020-10-20 09:24:14 -07:00
qctecmdr
4ed01e9865 Merge "msm: kgsl: Update the sequence to resume stalled SMMU on no GMU devices" 2020-10-20 09:24:13 -07:00
qctecmdr
248ae1ef4f Merge "cnss2: Add debug dump for Wlan FW PBL and SBL for HST" 2020-10-20 09:24:13 -07:00
Sarthak Garg
5dc9da83a5 mmc: host: Use request queue pointer for mmc crypto
To use block crypto based inline encryption mechanism
storage device driver should create a keyslot manager
and register it with device request queue. To achieve this
pass request queue pointer during host controller initialization
where request queue can be updated with keyslot manager.

Change-Id: I71f0005a1ad8867b6210e92878b8c112d436688e
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
2020-10-20 00:57:31 -07:00
qctecmdr
4cf5de7504 Merge "rpmsg: glink: do not break from interrupt handler" 2020-10-19 19:06:17 -07:00
qctecmdr
977809564c Merge "cnss2: Wait for RDDM if device is already in bad state" 2020-10-19 19:06:17 -07:00
qctecmdr
6d38e358c5 Merge "defconfig: Enable pil nodes on sdxlemur perf" 2020-10-19 19:06:16 -07:00
qctecmdr
0ffdcaf93c Merge "net: qrtr: Use alloc_skb_with_frags for backup memory" 2020-10-19 19:06:16 -07:00
qctecmdr
32ca277521 Merge "qcom: wdog: fix static analyzer reported issue in watchdog core" 2020-10-19 16:25:27 -07:00
Melody Olvera
3674e9ac35 defconfig: Enable pil nodes on sdxlemur perf
Enable pil node driver on perf for sdxlemur

Change-Id: Ib77e294e7b134dc44c7f3ff2d3f45de27a09597b
Signed-off-by: Melody Olvera <molvera@codeaurora.org>
2020-10-19 10:55:29 -07:00
Deepak Kumar Singh
d1ce922a2b rpmsg: glink: do not break from interrupt handler
If receive callback fails, returning error can cause interrupt
handler to exit. if old interrupts have been missed glink may
not read new packets from rx fifo.

Print error message if callback fails but do not return any error
to interrupt handler so that it can continue reading pending data in
rx fifo even if old interrupts were missed and no new interrupt is
coming from remote host.

Change-Id: I1adec1e2ba7337008ecc2d71bf5f96c331a22695
Signed-off-by: Deepak Kumar Singh <deesin@codeaurora.org>
2020-10-19 19:02:30 +05:30
qctecmdr
1baf48e18b Merge "msm: kgsl: Add missing registers in snapshot dump for holi gpu" 2020-10-19 03:31:30 -07:00
qctecmdr
797e04bfa4 Merge "mmc: Enable clk scaling for cqe" 2020-10-19 03:31:29 -07:00
qctecmdr
2777a719d6 Merge "soc: qcom: smem: increase smem hosts max count" 2020-10-19 03:31:29 -07:00
qctecmdr
63fbc8ffb1 Merge "mmc: sdhci-msm: Pass min and max voltage values to enable regulators" 2020-10-19 03:31:29 -07:00
qctecmdr
819fc38366 Merge "net/embms-kernel : EMBMS Tunneling Module" 2020-10-19 03:31:28 -07:00
qctecmdr
9cd07da8bf Merge "icnss2: Avoid sending fw down uevent to wlan driver twice" 2020-10-19 03:31:28 -07:00
Pankaj Gupta
a2cb531ffa msm: kgsl: Skip SP_INST_TAG and SP_INST_DATA dump in snapshot for A6xx
For A6XX targets skip dumping of SP_INST_TAG and SP_INST_DATA to fix
race in responding crashdumper status register through host path, when
crashdumper is busy reading SP data.

Change-Id: I8eb5647cefdba23571acc21f682782cfbf944eb1
Signed-off-by: Pankaj Gupta <gpankaj@codeaurora.org>
2020-10-19 02:03:47 -07:00
Mukesh Ojha
906421edbe qcom: wdog: fix static analyzer reported issue in watchdog core
Code static analyzer reports 'pivot' variable is uninitialized.
Let's fix this by initializing it with NULL and add necessary
checks.

Change-Id: I2aa521002ea55fa1e44b3ce17262a9093dd130a0
Signed-off-by: Mukesh Ojha <mojha@codeaurora.org>
2020-10-19 14:29:14 +05:30
Deepak Kumar Singh
9228043d74 soc: qcom: smem: increase smem hosts max count
Increase max host count to 14, inorder to accommodate newly
added sybsystem wpss with smem host id 13.

Change-Id: I48c7e576d3478bdc4645c44aa435900f3eaaa2c4
Signed-off-by: Deepak Kumar Singh <deesin@codeaurora.org>
2020-10-19 11:53:06 +05:30
Indira Biruduraju
d4e6b209bd msm: kgsl: Add missing registers in snapshot dump for holi gpu
Add missing registers in snapshot dump collected
at the time of GPU hang for holi gpu.

Change-Id: I90c5a8a001c3fbfdd0e8b2359bc719d779e6545a
Signed-off-by: Indira Biruduraju <ibirudur@codeaurora.org>
2020-10-18 22:14:53 -07:00
Santosh Mardi
8616e29d2c drivers: soc: qcom: fix incorrect updation of pmu cache flag in CPU_PM_EXIT
rimps_memlat driver will cache PMU counter values when cpu
is going down in hotplug path and also when CPU is entering
lpm. Once the PMU counter values are saved to the shared memory,
cache valid bit is set, and it is cleared when cpu comes back online
or exit from lpm.

RIMPS expects the PMU cache flag to be valid, when cpu is offline
or entered lpm. Observed a race when the hotplug is in progress
and that particular cpu can enter and exit lpm. The current
implementation clears the cache flag during lpm exit without
checking the cpu hotplug status. Once hotplug is complete, core
goes offline and the status flag will remain in incorrect state
indicating cache area is invalid, which will cause RIMPS to read
PMU counter values directly from hardware which will result in APB
read errors.

When hotplug is in progress, do not set status flag to
PMU_CACHE_INVALID in CPU_PM_EXIT path.

Change-Id: I17947ad93eeef99b2148e873dc719622aa372b7c
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
2020-10-17 18:36:04 +05:30
Santosh Mardi
67838f80cd drivers: soc: qcom: allow setup of pmu events during hotplug
Setup pmu counter functions of rimps memlat driver check cpu_is_hp
flag before creating counters, and the setup of pmu counters will
be called in two places one in probe and other when cpu is coming
up from hotplug path.

The hotplug path will clear cpu_is_hp after the pmu setup calls are
issued, but pmu setup function will not create pmu events as the
cpu_is_hp flag not cleared at this point, this results in pmu
counters not getting setup even cpu is up from the hotplug path.

Add a parameter to these functions indicating from which path these
are called and update the logic accordingly to allow creation of
pmu events when core is coming up.

Change-Id: I8bf8d52d91d14ab3f4d837271055f03e704e98a0
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
2020-10-17 18:36:03 +05:30
Santosh Mardi
cbcfe29a9d drivers: soc: qcom: use hw counter values for PMU snapshot to RIMPS
RIMPS memlat driver reads the current PMU counter value
using perf_event_read_local() API at the time of core
going offline or entering LPM and saves the current
snapshot to a shared memory for access by RIMPS.

RIMPS reads these values from the shared memory when
core is offline or in LPM state, and reads directly
from PMU hardware when core is online. The value read
from hardware and the one read from shared memory are
going out of sync because perf event driver limits the
counting range of PMU counter to half of the total range
supported by hardware, and it configures the counter to
start counting from midpoint at the time of counter reset
and upon overflow. It keeps adding the delta read from
hardware counters to software maintained counters and it
returns the same through perf_event_read API.
As this is not the exact same value as what is read from
hardware counters, the values read by RIMPS from shared
memory are going out of sync.

To address this get the current snapshot of hardware counter
value from prev_count member of hw_perf_event structure which
is part of perf_event structure, and store that to shared memory.

Change-Id: I71f416270a02f7925b16e576f637cf3579fec6ce
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
2020-10-17 18:35:52 +05:30
Santosh Mardi
2cb80d18ee drivers: soc: qcom: code clean up for rimps_memlat driver
Remove unused variable in hotplug path.

Change-Id: Ida006e8f39adc741ee63f63cdddcb51ddd2804f1
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
2020-10-17 03:24:43 -07:00
Santosh Mardi
dc4268916b drivers: soc: qcom: Handle CPU_PM_ENTER_FAILED notification
Mark PMU cache invalid if CPU_PM_ENTER fails.

Change-Id: Ieb2d34fcd94b99972443a3ade0458f9955281ffe
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
2020-10-17 03:24:21 -07:00
qctecmdr
d77ee90deb Merge "defconfig: msm: Enable qfprom_sys for Lahaina GKI" 2020-10-16 22:07:17 -07:00
qctecmdr
03e52f59a8 Merge "clk: qcom: debugcc: Update register offset for debug mux" 2020-10-16 18:49:20 -07:00
qctecmdr
e12ac54b46 Merge "defconfig: sdxlemur: Enable RPMh and GPIO regulators" 2020-10-16 18:49:19 -07:00
qctecmdr
f11438db40 Merge "defconfig: sdxlemur: Enable LLCC driver on sdxlemur" 2020-10-16 18:49:19 -07:00
Jay Jayanna
8bdd8b34c3 net: qrtr: Use alloc_skb_with_frags for backup memory
Use alloc_skb_with_frags for skb allocation to keep it uniform
throughout the rx path.

Change-Id: Id38eeea0a7d422b50c1ad6a90b9b569f26c45917
Signed-off-by: Jay Jayanna <jayanna@codeaurora.org>
2020-10-16 16:41:08 -07:00
Chris Lew
3e4aa12f4a net: qrtr: Add backup skb pool
Add a pool of SKBs that can be used when the system is in low memory
conditions. This pool will be shared between all nodes and replenished
by a worker function.

Change-Id: I639a9ac76db726dc8ad46b12d3b3d560c674939c
Signed-off-by: Chris Lew <clew@codeaurora.org>
2020-10-16 16:36:09 -07:00
Yue Ma
9e973e9fb6 cnss2: Wait for RDDM if device is already in bad state
When invoke cnss_force_collect_rddm(), if device is already in bad
state, wait till dump collection is completed.

Change-Id: Ic3d907bd512bb8ca99f88baf7a8d38f0c00cfe64
Signed-off-by: Yue Ma <yuem@codeaurora.org>
2020-10-16 10:48:29 -07:00
Melody Olvera
9cc45909c1 defconfig: sdxlemur: Enable LLCC driver on sdxlemur
This change enables LLCC driver on sdxlemur.

Change-Id: Ife2eb2c8ea5c4b5190cc58f882a72c525f6b0163
Signed-off-by: Melody Olvera <molvera@codeaurora.org>
2020-10-16 10:36:36 -07:00
Jeevan Shriram
c2d1b1bf9e drivers: llcc: Add LLCC driver for sdxlemur target
Add Last Level Cache Controller (LLCC) driver for sdxlemur platform.

Change-Id: I5fe907c6ed6dd2863e6488dac42e0c352ca48f48
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
2020-10-16 10:36:29 -07:00
Melody Olvera
f7101cee8b drivers: llcc: Allow configurations with no broadcast hardware
Previous iterations of the llcc driver did not account for caches with
no llcc broadcast hardware. This fixes this issue.

Change-Id: I221d0d65d17c34645cd1a4070737fe9bebfa4b16
Signed-off-by: Melody Olvera <molvera@codeaurora.org>
2020-10-16 10:32:29 -07:00
qctecmdr
1ca2f08101 Merge "msm-perf: Removed game active status node" 2020-10-16 10:09:28 -07:00
qctecmdr
557b8f8282 Merge "usb: f_gsi: Memory optimization for buffers on gsi for low MEM variants" 2020-10-16 10:09:28 -07:00
qctecmdr
c8b9369a28 Merge "USB: f_fs: Fix epfile crash during composition switch" 2020-10-16 10:09:27 -07:00
qctecmdr
cd758fb1b9 Merge "usb: dwc3-msm: Add interconnect bus voting through dt-node" 2020-10-16 10:09:26 -07:00
qctecmdr
060b3e941e Merge "net: config: Enabling SYN_COOKIES config option for lahaina target" 2020-10-16 10:09:26 -07:00
qctecmdr
6e67ceb99f Merge "defconfig: holi-gki: Enable CDSPRM driver" 2020-10-16 10:09:26 -07:00
qctecmdr
ce9c398026 Merge "input: touchscreen: mxt: refine power on/off flow" 2020-10-16 10:09:26 -07:00
Carter Cooper
8025323237 msm: kgsl: Clear ddr_table pointer after free
Clear the table pointer after it is freed to make sure
it doesn't get freed again.

Change-Id: Ica693a048fd76473a3937084c87f3631ef5b27dd
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
2020-10-16 08:01:48 -07:00
Naveen Yadav
25738f2916 clk: qcom: debugcc: Update register offset for debug mux
Update the register offsets for the debug mux to measure
the clock frequency correctly.

Change-Id: I329f3f3416d6b097e0fc38e72d136a5b21db7049
Signed-off-by: Naveen Yadav <naveenky@codeaurora.org>
2020-10-16 18:59:02 +05:30
Paras Singh Jain
5f73483da2 net/embms-kernel : EMBMS Tunneling Module
This module is used to tunnel multicast
packets received on an interface to WLAN
clients which have registered for these
packet streams. Mainly used to tunnel
EMBMS packets received on TMGI streams.

Change-Id: I1cea29bff192d375317dda3d1baebb594e0b9c39
Acked-by: Raju Velpula <rvelpula@qti.qualcomm.com>
Signed-off-by: Paras Singh Jain <parassin@codeaurora.org>
2020-10-16 18:23:27 +05:30
Pradeep P V K
45a05399cf mmc: sdhci-msm: Pass min and max voltage values to enable regulators
Pass minimum and maximum voltage values while enabling regulators.

Change-Id: I3de7f343cd0d8fd1953fa5d091c411c013a0dd29
Signed-off-by: Pradeep P V K <ppvk@codeaurora.org>
2020-10-16 04:46:04 -07:00