Move adreno_clear_pending_transactions to the target specific code.
Besides getting rid of some ADRENO_REG ambiguity and the need for
target specific masks in the gpudev this also provides some clarity
for a6xx since none of the GMU or RGMU targets end up using this
function in the first place so we can not worry about those and
focus on the a5xx/a6xx targets that do need it.
Change-Id: Ic0dedbadbc7927247c84d446664273c6464d07f5
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
This ensures that two concurrent writers through iptables-restore
cannot overwrite each other. Fixes the following-
<6> Unable to handle kernel paging request at
virtual address 006b6b6b6b6b6bc5
<6> [006b6b6b6b6b6bc5] address between user
and kernel address ranges
<2> pc : ipt_do_table+0x3b8/0x660
<2> lr : ipt_do_table+0x31c/0x660
<2> Call trace:
<2> ipt_do_table+0x3b8/0x660
<2> iptable_mangle_hook+0x58/0xf8
<2> nf_hook_slow+0x48/0xd8
<2> __ip_local_out+0xf4/0x138
<2> __ip_queue_xmit+0x348/0x3a0
<2> ip_queue_xmit+0x10/0x18
<2> __tcp_transmit_skb+0x734/0xaa8
<2> __tcp_retransmit_skb+0x5b8/0x930
<2> tcp_send_loss_probe+0x19c/0x300
<2> tcp_write_timer_handler+0x14c/0x238
<2> tcp_write_timer+0x74/0xa0
<2> call_timer_fn+0xc0/0x1c0
<2> run_timer_softirq+0x2f8/0xa30
<2> __do_softirq+0x1dc/0x384
This enforces the cleanup of the old entries under the xt_table lock.
CRs-fixed: 2612021
Change-Id: If721ceb7891e58847eae5c1ad9c5e9aea4c569e3
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
To use block crypto based inline encryption mechanism
storage device driver should create a keyslot manager
and register it with device request queue. To achieve this
pass request queue pointer during host controller initialization
where request queue can be updated with keyslot manager.
Change-Id: I71f0005a1ad8867b6210e92878b8c112d436688e
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
If unload app was failed due to EBUSY, qseecom will not free
app list entry, but just restore app ref_cnt and return EBUSY
to client.
Change-Id: If7b20b52690a34ba9cf1b3c3e96f84583d221dec
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
Few alpha PLLs would require to be able to slew in the same VCO mode, which
means the PLL would be able to update the new frequency L value without
turning it off. But to be support this feature the PLL needs to calibrated
at the mid of the VCO range and then enabled.
Add support for dynamic update in which the frequency can be changed
without turning off the PLL. and also Update list_register operation
to read the pll offset defined in PLL register map to avoid mismatch
alpha PLL.
Change-Id: Idbb374be8710cdcd80ab3c4ed57f89f00ed15d23
Signed-off-by: Taniya Das <tdas@codeaurora.org>
If receive callback fails, returning error can cause interrupt
handler to exit. if old interrupts have been missed glink may
not read new packets from rx fifo.
Print error message if callback fails but do not return any error
to interrupt handler so that it can continue reading pending data in
rx fifo even if old interrupts were missed and no new interrupt is
coming from remote host.
Change-Id: I1adec1e2ba7337008ecc2d71bf5f96c331a22695
Signed-off-by: Deepak Kumar Singh <deesin@codeaurora.org>
For A6XX targets skip dumping of SP_INST_TAG and SP_INST_DATA to fix
race in responding crashdumper status register through host path, when
crashdumper is busy reading SP data.
Change-Id: I8eb5647cefdba23571acc21f682782cfbf944eb1
Signed-off-by: Pankaj Gupta <gpankaj@codeaurora.org>
Code static analyzer reports 'pivot' variable is uninitialized.
Let's fix this by initializing it with NULL and add necessary
checks.
Change-Id: I2aa521002ea55fa1e44b3ce17262a9093dd130a0
Signed-off-by: Mukesh Ojha <mojha@codeaurora.org>
Increase max host count to 14, inorder to accommodate newly
added sybsystem wpss with smem host id 13.
Change-Id: I48c7e576d3478bdc4645c44aa435900f3eaaa2c4
Signed-off-by: Deepak Kumar Singh <deesin@codeaurora.org>
Add missing registers in snapshot dump collected
at the time of GPU hang for holi gpu.
Change-Id: I90c5a8a001c3fbfdd0e8b2359bc719d779e6545a
Signed-off-by: Indira Biruduraju <ibirudur@codeaurora.org>
rimps_memlat driver will cache PMU counter values when cpu
is going down in hotplug path and also when CPU is entering
lpm. Once the PMU counter values are saved to the shared memory,
cache valid bit is set, and it is cleared when cpu comes back online
or exit from lpm.
RIMPS expects the PMU cache flag to be valid, when cpu is offline
or entered lpm. Observed a race when the hotplug is in progress
and that particular cpu can enter and exit lpm. The current
implementation clears the cache flag during lpm exit without
checking the cpu hotplug status. Once hotplug is complete, core
goes offline and the status flag will remain in incorrect state
indicating cache area is invalid, which will cause RIMPS to read
PMU counter values directly from hardware which will result in APB
read errors.
When hotplug is in progress, do not set status flag to
PMU_CACHE_INVALID in CPU_PM_EXIT path.
Change-Id: I17947ad93eeef99b2148e873dc719622aa372b7c
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
Setup pmu counter functions of rimps memlat driver check cpu_is_hp
flag before creating counters, and the setup of pmu counters will
be called in two places one in probe and other when cpu is coming
up from hotplug path.
The hotplug path will clear cpu_is_hp after the pmu setup calls are
issued, but pmu setup function will not create pmu events as the
cpu_is_hp flag not cleared at this point, this results in pmu
counters not getting setup even cpu is up from the hotplug path.
Add a parameter to these functions indicating from which path these
are called and update the logic accordingly to allow creation of
pmu events when core is coming up.
Change-Id: I8bf8d52d91d14ab3f4d837271055f03e704e98a0
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
RIMPS memlat driver reads the current PMU counter value
using perf_event_read_local() API at the time of core
going offline or entering LPM and saves the current
snapshot to a shared memory for access by RIMPS.
RIMPS reads these values from the shared memory when
core is offline or in LPM state, and reads directly
from PMU hardware when core is online. The value read
from hardware and the one read from shared memory are
going out of sync because perf event driver limits the
counting range of PMU counter to half of the total range
supported by hardware, and it configures the counter to
start counting from midpoint at the time of counter reset
and upon overflow. It keeps adding the delta read from
hardware counters to software maintained counters and it
returns the same through perf_event_read API.
As this is not the exact same value as what is read from
hardware counters, the values read by RIMPS from shared
memory are going out of sync.
To address this get the current snapshot of hardware counter
value from prev_count member of hw_perf_event structure which
is part of perf_event structure, and store that to shared memory.
Change-Id: I71f416270a02f7925b16e576f637cf3579fec6ce
Signed-off-by: Santosh Mardi <gsantosh@codeaurora.org>
Use alloc_skb_with_frags for skb allocation to keep it uniform
throughout the rx path.
Change-Id: Id38eeea0a7d422b50c1ad6a90b9b569f26c45917
Signed-off-by: Jay Jayanna <jayanna@codeaurora.org>
Add a pool of SKBs that can be used when the system is in low memory
conditions. This pool will be shared between all nodes and replenished
by a worker function.
Change-Id: I639a9ac76db726dc8ad46b12d3b3d560c674939c
Signed-off-by: Chris Lew <clew@codeaurora.org>
When invoke cnss_force_collect_rddm(), if device is already in bad
state, wait till dump collection is completed.
Change-Id: Ic3d907bd512bb8ca99f88baf7a8d38f0c00cfe64
Signed-off-by: Yue Ma <yuem@codeaurora.org>
Previous iterations of the llcc driver did not account for caches with
no llcc broadcast hardware. This fixes this issue.
Change-Id: I221d0d65d17c34645cd1a4070737fe9bebfa4b16
Signed-off-by: Melody Olvera <molvera@codeaurora.org>
