This changes swaps the order of encode initialization between
wb and dsi displays. This ensures that wb encoder is registered
before DSI/DP encoder in mode_list and it allows single CRTC
to loop through WB encoder before other encoder during mirror mode
topology like CWB use case. With existing order of encoder list, CWB
flush is happening after primary commit flush which is causing cwb
failures when there is a cpu latency.
Change-Id: I24d6b4f27271d46e9743d17a624ac7e0930f7474
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
This change updates the block offsets for concurrent writeback
blocks and fixes the register dumping logic.
Change-Id: I41b540773fea60e66cab5d476dff1a19b4f4b3db
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Add changes to commit and decrement only those
hardware resources which are required for the modeset.
Timeline of Commit C1 with CWB modeset:
---> Atomic_check
Primary encoder has allocated required HW resources.
CWB encoder has allocated required HW resources.
---> Atomic_commit
On primary encoder, connector is seamless hence
there is no virt_modeset call.
On CWB encoder, there is virt_mode_set call
and during commit HW blocks there is unconditional
decrement for all the HW blocks with rsvp_nxt.
This change ensures hardware blocks are available during
dp display mode validations.
Change-Id: Ifd9439cfc96e727c3093af5f47802c8367775cd7
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
Avoid corrupting the cb_list by setting timestamp before signal.
The fence driver changed in msm-5.4 by creating a union for the
fence cb_list, timestamp, and rcu. Therefore only one of these
fields can be used at a time. Fence driver will take care of
setting the timestamp during dma_fence_signal after it has
cached the cb_list. Also, use fence framework API to set fence
error instead of modifying the dma_fence struct directly.
Change-Id: I58dbaa495027cb575f4f0b03275ca4aa551ecacb
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Avoid exposing any uninitialized data when setting up the
interrupt tables.
Change-Id: I00d3dc8b5acc843401148585a129fde58e326beb
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This change programs dither based on user mode input data and
reprograms the dither when device comes out of power collapse.
Change-Id: I83be20c8eb2dc2221cc57cd2395f6512338ff6ef
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Update the definition of the atomic_check function for
DisplayPort connectors to align with the DRM upstream changes.
Change-Id: Id942c8ef16ae773540c4bc7221e0b784354a527c
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Update sde_drm.h header to use the display techpack path for
kernel-5.4.
Change-Id: I2b7dcbbde8128eece7a2a8a652f9f7c427b38110
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Fix and decouple widebus-enable flag from dsc_en for dp.
Change-Id: I2d31bc367f007d4c918babc1c051492544bbb05c
Signed-off-by: Xiaowen Wu <wxiaowen@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Update the mode validation logic by halving the mode clock
when widebus is enabled.
Change-Id: I8f060d8b60403aa5020496983bec0b3e2878b08b
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
When DP is working in MST mode, reading native EDID from MST
branch is not a valid operation.
Change-Id: I297d2b25b2c3166d68ef3eba941ca787d8bce8d3
Signed-off-by: Xiaowen Wu <wxiaowen@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
In the current kernel version calling kthread_mod_delayed_work
in irq context is not allowed. Due to this resource control state
change to idle on frame done is handled in display thread context.
Change-Id: I709f7e04ac23d7dde72cea1c19d3767b6abc147e
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
The original SB DMA last command logic results in multi
feature sets being applied across different frames. Update
the SB DMA logic to do a single last command per CTL path
to ensure all features using SB DMA can get applied in the
same frame.
Change-Id: Ida837765c0f018b0e03afb0a33ece625a0df81eb
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
The current implementation of DSPP GAMUT + IGC programming rely on
SBDMA for programming. This will cause GAMUT + IGC to be
unprogrammable on derivative Lahaina chipsets that do not have SBDMA
support.
Update the SBDMA handling to more intelligently check if SBDMA is
present, and fallback to DBDMA module where possible.
Change-Id: I89d07e38459ab59b96c69558178b8e97062ed93d
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
A new LUTDMA opcode is added to LUTDMA V2 to speed up certain LUT
programming. This change updates the SSPP Gamut LUT programming using
the new opcode and new LUT BUS.
Change-Id: I8b88483dc3acbfcdbd6f441bc2105f4368fa42bb
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Add new implementation for DSPP GAMUT and IGC features using
newly added SB LUTDMA.
Change-Id: Iebc099351fde058d7f0e20a9e256bcd71c557506
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
A new LUTDMA HW instance has been added to support programming of
SB features via LUTDMA. This change adds corresponding support for
the new SB LUTDMA, including catalog parsing, reg_dma init/deinit/ops
updates and new opcode support.
Change-Id: I0fed7a6e93cd96fe9fe562d2470a8789b161d1bc
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Extend unified flush bit support to control new DSPP
SB LUTDMA bit.
Change-Id: Iba941a4bcd140ceb88e49ab83700c4baef804e0f
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Remove colorspace property from connector until upstream
changes are merged and we can validate the related features.
This change is required to enable DP bring up activities.
Change-Id: I6c1af61732e572b2ffd16e0a323d08154aa83b53
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
In atomic test phase DSC Hw block should be allowed to be reserved
without checking the mode information. Mode information is not
available before bridge enable is called and this results into dsc
not programmed very first mode set.
Change-Id: Ia9ec9a3c9387e34a8bb1d98ee6932aef8725bc8c
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Reduce the cyclomatic complexity for installing CRTC properties.
Change-Id: I42572413713b3a079fb5edcaa25d9050b76adc6c
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
The clock framework nulls the clock hardware init data, after a variant
of clk_register is called on the clk_hw pointer. This results in a null
pointer dereference when we try to call set rate in the PLL prepare
function. The call can be a direct call to the function rather than
trying to access through the init_data pointer of the clk_hw.
Change-Id: I3613eea915d4f5620d7f0258ae391ad2ac624148
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Legacy HW that does not support pre-downscale capability will
incorrectly fail certain scaling checks. Fix those checks to
fully support HW without pre-downscaler.
Change-Id: I8f645bbff959e176c1d4d05a30a580113e320d4b
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
The pre-downscale capability is checked in multiple places
within sde_plane.c file. Add a helper function to check this
capability flag instead of manually checking this bit.
Change-Id: I21f818a9d81dd63e5eb3da248532904cfa55c838
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Add partial update handling for color processing features.
This will validate and set cp features for each frame if
applicable.
Change-Id: Id78c1f4ecbd74781c0c03c04efb528d6a8b91264
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Add atomic check handling in color processing framework.
This will check cp features during the validate phase.
Change-Id: I6d94316a749ad247aec0554c31fa56af6db61ab6
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Add support for absolute mdss addressing lutdma payload. This will
allow any mdss register to be programmed using lutdma.
Change-Id: I3af3a85182a75a0583c49c797d6adf99b6ba2ee7
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
This change enables the interface hw block to accept
64-bit compressed pixels. This configuration is enabled based
on hw capability. For current hw, this is required any time
the compressed pixels flow through the interface block,
whereas in the previous version of DPU hw this configuration
is only required for topology using 4 way dsc merge.
Change-Id: I7bf79d035dba5084c5057022a7fa1117479e8d52
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Defines should always have a single space between #define and
the keyword to allow for searching where these definitions are
located using grep.
Change-Id: I38778e789b12df8a7a22c22dd27152a5ab047405
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Currently the compression ratio is hard-coded to either 2:1 or
3:1 in several places. This is not sufficient for new compression
algorithms as they can support higher compression ratios.
Add support for calculating the compression ratios from the source
and target bpp thereby eliminating hard-coding.
Change-Id: I6383f3d0c781193d0a9ed74df5a95d8e856edb3d
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
