Commit graph

894,770 commits

Author SHA1 Message Date
qctecmdr
2b4e0cfccf Merge "defconfig: gen3auto: Enable QFPROM driver" 2021-01-25 06:19:18 -08:00
qctecmdr
3e2b3819e6 Merge "cnss2: Dump mhi debug registers on receiving mhi WAKE event cb" 2021-01-25 06:19:18 -08:00
Pavankumar Kondeti
a0f963c162 sched/walt: Improve the scheduler
This change is for general scheduler improvement.

Change-Id: I288fc9a8858cb29ae9c6993b398a349b4a8c7475
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
2021-01-25 19:02:41 +05:30
Veera Vegivada
e3418144c0 arm64: defconfig: Enable UFS controller for SA6155
Add support for UFS controller.

Change-Id: I39feb91b5f2e635d27a751c33bb07a703133debb
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2021-01-25 18:33:56 +05:30
Veera Vegivada
ede1f0a6db arm64: sdmsteppeauto: Enable OSM L3 interconnect driver
Enable OSM L3 interconnect driver so that consumers
can change the hardware state based on the usecase.

Change-Id: Ibb4156ff5adbf5c874951e781f41706828fa5751
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2021-01-25 18:31:30 +05:30
Veera Vegivada
84abd630f7 arm64: defconfig: Enable SM6150 interconnect driver
Enable the SM6150 interconnect driver so that consumers are
able to obtain their path handles properly.

Change-Id: Ie6b99d37f73b69dc375426d64e9148b9a64180f5
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2021-01-25 18:29:48 +05:30
qctecmdr
c8429d64fc Merge "cnss2: Add code to download qdss trace config" 2021-01-25 02:40:21 -08:00
qctecmdr
fb50822968 Merge "qseecom : Add support for fuse syscall" 2021-01-25 02:40:21 -08:00
qctecmdr
e92b33876b Merge "msm: kgsl: Enable some essential features for A680 GPU" 2021-01-25 02:40:21 -08:00
qctecmdr
5276cb9926 Merge "cnss2: Update GPIOs for wake capability disablement" 2021-01-25 02:40:20 -08:00
Jack Pham
c4f5b14f2b usb: f_gsi: Clean up low memory buffer size/depth definitions
Move the #ifdef CONFIG_USB_LOW_MEM_VARIANT conditionals from
to the f_gsi.h header and simplify the usages in the code to
use a single set of #defines.

Also add a redefinition of the ADPL buffer depth to 15 in
case of low memory variant.

Change-Id: I138ec69effd5ef38a6de95b8ce6a1f356d6079bb
Signed-off-by: Jack Pham <jackp@codeaurora.org>
2021-01-25 01:30:50 -08:00
Jishnu Prakash
de7005f054 regulator: qpnp-lcdb: Add support for NCP symmetry with LDO
Add a device tree property which enables NCP symmetry. This
configuration in HW enables the NCP voltage to follow LDO.

Change-Id: If44b049a3ecd031f111dcb8477166925a0d01914
Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
2021-01-25 14:30:06 +05:30
Hareesh Gundu
1f01e1f37d msm: kgsl: Enable IFPC feature for A635 GPU
IFPC stands for Inter-Frame Power Collapse.
Enable IFPC for A635 GPU for power saving purpose.

Change-Id: I989d90e76520e316a3200004a2d3e7e26f0a45a5
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
2021-01-25 13:27:50 +05:30
Zhiqiang Tu
2202e76aae defconfig: gen3auto: Enable QFPROM driver
Enable QFPROM to support NVMEM read/write.

Change-Id: I54dbc765a24b163f4cdb2f658a21ad95d842314f
Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
2021-01-24 23:46:01 -08:00
Yuanfang Zhang
59d75f4711 defconfig: enable qdss component for sdxnightjar
Enable qdss component ETM/STM/CTI/TPDM/TPDA/TMC on sdxnightjar.

Change-Id: I147b1078c7a524d9366cd769019461b344a1cfc7
Signed-off-by: Yuanfang Zhang <zhangyuanfang@codeaurora.org>
2021-01-25 15:33:17 +08:00
qctecmdr
52da8f55ee Merge "msm: kgsl: Add enable_signaling for timeline fence" 2021-01-24 22:54:19 -08:00
qctecmdr
cbef52ce19 Merge "power: smb358: Add support to make SMB358 driver GKI complaint" 2021-01-24 22:54:19 -08:00
Monika Singh
d9858f6b11 qseecom : Add support for fuse syscall
Add changes to support syscall to return fuse
configuration on the device. Also rename
function to improve redability.

Change-Id: Idec01fec75a5dd6a86ad6dc319d18129c4ec2740
Signed-off-by: Monika Singh <monising@codeaurora.org>
2021-01-25 10:42:24 +05:30
Hui Li
49644357e0 msm: kgsl: Enable some essential features for A680 GPU
Enable PREEMPTION, IFPC, CONTENT_PROTECT, IOCOHERENT
supports for sdmshrike platform.

Change-Id: I8238c4ac7fff6c607b0eafb9fdfab13cdf44003f
Signed-off-by: Hui Li <hul@codeaurora.org>
2021-01-24 19:39:11 -08:00
Zhiqiang Tu
f9bd900b8a i2c: virtio: Add snapshot of virtio i2c driver
Add snapshot of virtio i2c driver from msm-4.14.
This snapshot is taken as of msm-4.14 commit 972d72613cd1
("i2c: virtio: Fix return value issue of transfer function").

Change-Id: Idb4f6b5918f7d7237146d02839638b8a97a05c02
Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
2021-01-24 05:11:10 -08:00
qctecmdr
e168b52f6b Merge "msm: pcie: Add tcsr configuration" 2021-01-23 23:36:22 -08:00
qctecmdr
b368317cea Merge "clk: qcom: gpucc-yupik: Remove GPUCC PLL0 configuration from HLOS" 2021-01-23 23:36:22 -08:00
Hardik Kantilal Patel
2273a9e6c9 ICNSS2: Enable Runtime PM feature for Moselle
Enable Runtime PM feature for Moselle.

Change-Id: I210a77052a25067802ca74eb82ad2a045d4c7dbc
Signed-off-by: Hardik Kantilal Patel <hkpatel@codeaurora.org>
2021-01-23 19:08:33 +05:30
qctecmdr
c522f59658 Merge "iommu/arm-smmu: Fix SMR mask extraction for bootloader programmed SMRs" 2021-01-22 21:12:24 -08:00
qctecmdr
22e7b8f5e9 Merge "msm: pcie-ep: Use default PCIe CLKREQ# settings" 2021-01-22 21:12:24 -08:00
qctecmdr
8349627940 Merge "msm: cvp: Support handling cp camera buffer" 2021-01-22 17:31:16 -08:00
qctecmdr
ccffb23bfa Merge "msm: kgsl: Enable Preemption on A635 GPU" 2021-01-22 17:31:16 -08:00
qctecmdr
4d6ec09334 Merge "defconfig: Configure MaxPower to 900mA" 2021-01-22 17:31:15 -08:00
Isaac J. Manjarres
8b27d2333a iommu/arm-smmu: Fix SMR mask extraction for bootloader programmed SMRs
When extracting the mask for an SMR that was programmed by the
bootloader, the SMR.valid field is also extracted and is treated
as part of the mask. This causes issues when removing an SMMU
master, as removing the master involves constructing an SMR
entry with the mask and SID without the valid bit set and writing
that value to the SMR. However, since the valid bit was part of
the mask, the SMR will still be valid.

Instead, remove the valid bit from the raw SMR value that is used
for extracting the SMR mask.

Change-Id: Iccada2c474b196200ae1b56eb9faa9cb026f5ef1
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2021-01-22 15:41:13 -08:00
Siddartha Mohanadoss
7328656346 msm: pcie-ep: Use default PCIe CLKREQ# settings
Use default settings for CLKREQ# from pinctrl DTSI.
Configuring the GPIO in the HLOS driver is causing the
PCIe controller to go down and any DBI access is causing
a NOC error. Since this GPIO is not configured during
resume or sleep the driver can rely on the pinctrl settings
that is programmed as part of the TLMM driver initialization
of the GPIO as default.

Change-Id: Ib6a62e6aa471c39858302fdc0e575fc7ab5abff4
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
2021-01-22 15:33:35 -08:00
qctecmdr
78bb563bf8 Merge "input: qcom-hv-haptics: check playing effect pointer in IRQ handler" 2021-01-22 13:46:45 -08:00
qctecmdr
c1cc7c0229 Merge "usb: core: Reduce resume signalling time for devices behind external hub" 2021-01-22 13:46:44 -08:00
qctecmdr
e9b58393fb Merge "pinctrl: qcom: Expose ufs_reset as gpio on sm6150" 2021-01-22 13:46:44 -08:00
qctecmdr
6bfe888368 Merge "defconfig: Add configs to enable cpufreq/devfreq" 2021-01-22 13:46:44 -08:00
qctecmdr
63121c3d1e Merge "defconfig: gen3auto: Enable QCOM_SCM" 2021-01-22 13:46:44 -08:00
qctecmdr
a8e20ab52c Merge "defconfig: quinvmauto: Enable hab and peripheral drivers" 2021-01-22 13:46:43 -08:00
qctecmdr
0ef96ce882 Merge "mmc: sdhci-msm: Always set max_busy_timeout as zero" 2021-01-22 13:46:43 -08:00
qctecmdr
eb36342966 Merge "netfilter: Add reset_timer logic to timers" 2021-01-22 13:46:43 -08:00
qctecmdr
e1eeda2440 Merge "icc: dt-bindings: add endpoint IDs for interconnects for SM6150" 2021-01-22 13:46:42 -08:00
Jagadeesh Kona
bbeeb65e4e clk: qcom: gpucc-yupik: Remove GPUCC PLL0 configuration from HLOS
Remove GPUCC PLL0 configuration from HLOS as this PLL would be
configured from Graphics FW.

Change-Id: I97e94d71c941c67dad9e0fe3f2a08d4b36f95103
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
2021-01-23 00:18:27 +05:30
qctecmdr
152d15378a Merge "coresight: cti: Solve boot up issue" 2021-01-22 10:04:02 -08:00
qctecmdr
1dd7418832 Merge "msm: kgsl: Fix nr_removed calculation while reducing pools" 2021-01-22 10:04:02 -08:00
qctecmdr
652039e88a Merge "msm: kgsl: Enable GMU BW scaling and update CP ROQ size" 2021-01-22 10:04:01 -08:00
qctecmdr
c23063ec72 Merge "serial:msm_geni_serial: Handling the cts counter in uart driver" 2021-01-22 10:04:01 -08:00
qctecmdr
f18fc34265 Merge "arm: defconfig: enable firmware loader helper" 2021-01-22 10:04:01 -08:00
qctecmdr
372a5f3f6d Merge "arm64: defconfig: Enable PDC device for sdmsteppeauto" 2021-01-22 10:04:00 -08:00
qctecmdr
7e44485813 Merge "drivers: thermal: Use lock before accessing thermal instance list" 2021-01-22 10:04:00 -08:00
Pranav Patel
55d32239a2 msm: kgsl: Add enable_signaling for timeline fence
Implement enable_signaling for timeline fence. Dma fence driver's
APIs such as dma_fence_add_callback() use enable_signaling for
fence status and correct return value. Implementing this fix
scenarios such as dma_fence_add_callback() returning invalid
return value when timeline has been moved ahead.

Change-Id: Iaad8bf2801802216050e70c1b8ee1e0b2ec87a5f
Signed-off-by: Pranav Patel <pranavp@codeaurora.org>
2021-01-22 23:08:15 +05:30
Nitesh Gupta
b2356dc135 msm: pcie: Add tcsr configuration
Add support for reading tcsr configuration from device tree and
configuring tcsr register dynamically.
This change for supporting sa8195p PCIe1. The default PCIe linkage
status of PCIe1 and 2 on sa8195p is:
PCIe1: not enabled
PCIe2: x4 lane
When config the register TCSR_PCIEPHY_LINK_CONFIG to 0(default 1),
the linkage status becomes:
PCIe1: x2 lane
PCIe2: x2 lane
This change add the ability to read tcsr value from device tree.

Change-Id: Iac53f61a147a839772c8411993f3be233b142b56
Signed-off-by: Xiang Li <lixiang@codeaurora.org>
Signed-off-by: Nitesh Gupta <nitegupt@codeaurora.org>
2021-01-22 09:27:15 -08:00
Elson Roy Serrao
d0aefaf022 defconfig: Configure MaxPower to 900mA
Add the config entry to set the MaxPower to 900mA to accommodate
Super Speed and above.

Change-Id: I7e002b4942d1f5548c6d3281ac89e74f633b5723
Signed-off-by: Elson Roy Serrao <eserrao@codeaurora.org>
2021-01-22 07:56:05 -08:00