Commit graph

899,378 commits

Author SHA1 Message Date
qctecmdr
ddbef40a73 Merge "msm: kgsl: Retry process private open in a special failure case" 2021-07-09 06:01:36 -07:00
qctecmdr
cae2be6e8e Merge "clk: qcom: clk-alpha-pll: Update the steps to slew the Lucid PLL" 2021-07-09 06:01:36 -07:00
qctecmdr
a757adffe8 Merge "soc: qcom: Correct the modem data for wdog bite handler" 2021-07-09 06:01:35 -07:00
Taniya Das
fd141c2398 clk: qcom: clk-alpha-pll: Update the steps to slew the Lucid PLL
When PLL HW_UPDATE_LOGIC_BYPASS bit is not set then PLL can be
updated dynamically by setting the PLL_UPDATE bit in mode register
and hardware would clear the PLL_UPDATE automatically when
PLL_ACK_LATCH is asserted.

Change-Id: I1c568c9fdd37a554d71fc5c3d840a71e983baf60
Signed-off-by: Taniya Das <tdas@codeaurora.org>
2021-07-09 02:32:00 -07:00
Deepak Kumar
65e208cf89 msm: kgsl: Retry process private open in a special failure case
Currently, process private open/kgsl_open fails in case same pid
previous process private refcount is zero but destroy didn't
complete yet. In this failure case, as we are sure that destroy
is triggered and just pending to finish, retry process private
open again after some delay to ensure process private open is
successful.

Change-Id: I7cd8a2b7d64d9472121ffa8633d0621923f5ec89
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
2021-07-09 14:36:28 +05:30
qctecmdr
821dd9939b Merge "msm: sps: Correct descriptor fifo address to dump contents" 2021-07-09 01:51:15 -07:00
lijuang
dcb104f131 soc: qcom: Correct the modem data for wdog bite handler
Correct the modem data for wdog bite handler, otherwise it will access
a invalid subsys.

Change-Id: Iedd7b85597fa95d283d3a7b9bdd59c8a7c765792
Signed-off-by: lijuang <lijuang@codeaurora.org>
2021-07-08 23:54:59 -07:00
qctecmdr
c76c741a86 Merge "icnss2: Add Null check before dereferencing variables" 2021-07-08 18:06:02 -07:00
qctecmdr
38f07e2e36 Merge "msm: synx: Fix accessing uninitialized variable" 2021-07-08 18:06:02 -07:00
qctecmdr
581bc36999 Merge "mmc: core: Remove unnecessary scale debugfs entry" 2021-07-08 08:24:31 -07:00
qctecmdr
891649f939 Merge "usb: fix various gadget panics on 10gbps cabling" 2021-07-08 08:24:31 -07:00
qctecmdr
c519e10445 Merge "msm: pcie: update RC MPS based on MPSS" 2021-07-08 08:24:30 -07:00
qctecmdr
0889086dbb Merge "power: qpnp-qg: Add support to clear soh upon first profile load" 2021-07-08 08:24:30 -07:00
Rama Krishna Phani A
c76ce6f848 msm: sps: Correct descriptor fifo address to dump contents
Few clients of BAM will use SMMU for data transfers.
Assign correct descriptor fifo address for SMMU clients
of BAM while dumping contents.

Change-Id: I21584e6778315f51cac0d202d41f4c81a56fcbf0
Signed-off-by: Rama Krishna Phani A <rphani@codeaurora.org>
2021-07-08 18:50:27 +05:30
Ajay Prathi
f094710be7 msm: sps: Use iomem attribute for base address
Clients may use ioremap api to obtain the bam base address.
Add iomem attribute to the base address field
in the public SPS structure to avoid type casts.

Change-Id: Iba2ec1a9d84c3d57e2ce314ba9dc0b81644db2fb
Signed-off-by: Ajay Prathi <aprathi@codeaurora.org>
2021-07-08 18:50:19 +05:30
qctecmdr
5b3872731b Merge "sched: Improve the scheduler" 2021-07-07 23:18:38 -07:00
Sumukh Hallymysore Ravindra
1e954f343d msm: synx: Fix accessing uninitialized variable
Change fixes accessing possible uninitialized
variable in an error log.

Change-Id: Ibc72faddb7073c0408c2c822991b9835992dffaf
Signed-off-by: Sumukh Hallymysore Ravindra <shallymy@codeaurora.org>
2021-07-07 22:01:14 -07:00
Vijay Patil
550d642faa icnss2: Add Null check before dereferencing variables
Add Null check before dereferencing dev for set FW log mode,
force wake request & force wake response. Add ERR_OR_NULL check
for wpss load API gets called for wpss subsystem. Check for qdss
memory segment length.

Change-Id: Id4a43fa9ae332faa7f5741f338d985db8272d17a
Signed-off-by: Vijay Patil <vijaylil@codeaurora.org>
2021-07-07 14:46:46 +05:30
Pratham Pratap
f2f05457ef usb: gadget: Restart USB session if start xfer fails for ep0
Currently driver is just proceding further if start xfer times
out for ep0. Start xfer failing for ep0 indicates that the
controller is already in bad state and it can access unmapped
address leading to SMMU fault. Prevent this by marking this as
an error event and restart USB session.

Change-Id: Ia46387e16a79318ad945079ced7209a8f2bf47ef
Signed-off-by: Pratham Pratap <prathampratap@codeaurora.org>
2021-07-07 02:04:03 -07:00
Lingutla Chandrasekhar
34afd1c16e sched: Improve the scheduler
This change is for general scheduler improvements.

Change-Id: I37d6cb75ca8b08d9ca155b86b7d71ff369f46e14
Signed-off-by: Lingutla Chandrasekhar <clingutla@codeaurora.org>
2021-07-07 10:51:31 +05:30
Kavya Nunna
c0b667d58c power: qpnp-qg: Add support to clear soh upon first profile load
When the battery profile is loaded first time, update the
clear soh property so that soh algorithm can clear stored
parameters.

Change-Id: Idfc25c589f8422b76768229e52dab7d670c6b231
Signed-off-by: Kavya Nunna <knunna@codeaurora.org>
2021-07-06 22:19:19 -07:00
Kavya Nunna
a459581244 include: dt-bindings: Add iio-property for clear soh
Add iio property for clear soh to update userspace
on first profile load.

Change-Id: I7a9c2cf886ad7da76f6156c3ac12828bf37fe78a
Signed-off-by: Kavya Nunna <knunna@codeaurora.org>
2021-07-06 22:18:06 -07:00
Sarthak Garg
52da491c29 mmc: core: Remove unnecessary scale debugfs entry
Current scale debugfs entry is quite unstable and used barely.
Hardware cmd timeout and some other issues are being seen when trying to
modify the scale entry.
Remove unnecessary scale debugfs entry to avoid such issues.

Change-Id: I9486a9fe7498ba1855153202415fca80debb13f9
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
2021-07-06 21:30:41 -07:00
Maciej Żenczykowski
478702145f usb: fix various gadget panics on 10gbps cabling
usb_assign_descriptors() is called with 5 parameters,
the last 4 of which are the usb_descriptor_header for:
  full-speed (USB1.1 - 12Mbps [including USB1.0 low-speed @ 1.5Mbps),
  high-speed (USB2.0 - 480Mbps),
  super-speed (USB3.0 - 5Gbps),
  super-speed-plus (USB3.1 - 10Gbps).

The differences between full/high/super-speed descriptors are usually
substantial (due to changes in the maximum usb block size from 64 to 512
to 1024 bytes and other differences in the specs), while the difference
between 5 and 10Gbps descriptors may be as little as nothing
(in many cases the same tuning is simply good enough).

However if a gadget driver calls usb_assign_descriptors() with
a NULL descriptor for super-speed-plus and is then used on a max 10gbps
configuration, the kernel will crash with a null pointer dereference,
when a 10gbps capable device port + cable + host port combination shows up.
(This wouldn't happen if the gadget max-speed was set to 5gbps, but
it of course defaults to the maximum, and there's no real reason to
artificially limit it)

The fix is to simply use the 5gbps descriptor as the 10gbps descriptor,
if a 10gbps descriptor wasn't provided.

Obviously this won't fix the problem if the 5gbps descriptor is also
NULL, but such cases can't be so trivially solved (and any such gadgets
are unlikely to be used with USB3 ports any way).

Cc: Felipe Balbi <balbi@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Maciej Żenczykowski <maze@google.com>
Cc: stable <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20210609024459.1126080-1-zenczykowski@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Git-commit: 032e288097a553db5653af552dd8035cd2a0ba96
Change-Id: Ic90930c8ff99f2a3749c79a268f0a410827e485c
Signed-off-by: Elson Roy Serrao <eserrao@codeaurora.org>
2021-07-06 08:31:38 -07:00
qctecmdr
0d384b92bf Merge "cnss2: Add code to notify mhi about link down" 2021-07-06 05:09:13 -07:00
Tony Truong
52eb9e1439 msm: pcie: update RC MPS based on MPSS
Scale PCIe RC Max Payload Size (MPS) based on its capability
Max Payload Size Supported (MPSS). Configurating RC MPS to the
largest setting possible will help improve overall PCIe link
bandwidth performance.

Change-Id: Ice31cf0ab97fd7dd83736eea77e42ff00fb3148c
Signed-off-by: Tony Truong <truong@codeaurora.org>
2021-07-05 23:28:03 -07:00
Tony Truong
b96fd565f8 msm: pcie: add support to update MPS for all child PCI devices
Update Max Payload size (MPS) for all child PCI devices of RC.
Child PCI devices will have their MPS scaled to at most RC MPS.
Configuring all child PCI devices with the largest MPS possible
will help improve overall PCIe link bandwidth performance.

Change-Id: I871b49a5ec07d020a445a59f622ceec6061dfc26
Signed-off-by: Tony Truong <truong@codeaurora.org>
2021-07-05 23:18:51 -07:00
qctecmdr
3f7b291018 Merge "coresight: fix etr pice mode issue" 2021-07-05 22:49:49 -07:00
qctecmdr
5b9483c75b Merge "msm: kgsl: Add inode info in kgsl mem dump" 2021-07-05 18:35:51 -07:00
qctecmdr
ebd7f8e1c0 Merge "taskstats: properly account NR_KERNEL_MISC_RECLAIMABLE" 2021-07-05 03:02:08 -07:00
qctecmdr
1e9f7380d5 Merge "pinctrl: qcs404: update gpio, function and group binding" 2021-07-05 03:02:08 -07:00
qctecmdr
67683b3310 Merge "soc: wdog: Ensure missing user watchdog pet can trigger bite" 2021-07-05 03:02:08 -07:00
qctecmdr
ee417bda82 Merge "defconfig: sdxlemur: Enable DRM and GKI_HIDDEN_DRM_CONFIGS on sdxlemur" 2021-07-05 03:02:08 -07:00
qctecmdr
72b140fb68 Merge "Merge android11-5.4.86+ (e399f16) into msm-5.4" 2021-07-05 03:02:07 -07:00
qctecmdr
34c4a7f112 Merge "usb: dwc3: Add support of disable L1 in HS mode" 2021-07-05 03:02:07 -07:00
qctecmdr
7f2cb0175f Merge "mhi: core: Notify all mhi client's for PCIe link down recovery" 2021-07-05 03:02:07 -07:00
qctecmdr
b21450113f Merge "spi: spi-msm-geni: Store the wrapper dev handle for LE VM also" 2021-07-05 03:02:06 -07:00
qctecmdr
15f150f081 Merge "dt-bindings: msm: Add bindings for flash type" 2021-07-05 03:02:06 -07:00
qctecmdr
91c528605e Merge "soc: qcom: eud: Add support for different interrupt masks" 2021-07-04 21:57:40 -07:00
qctecmdr
d832036bda Merge "defconfig: sdxlemur: Enable configs for minidump" 2021-07-04 21:57:40 -07:00
qctecmdr
dfcaefd71c Merge "msm: mhi_dev: Disabling Ch Db Intr during MHI INIT phase" 2021-07-04 21:57:38 -07:00
Abhinab Abhinab
eac435a0a2 msm: mhi_dev: Disabling Ch Db Intr during MHI INIT phase
In order to tackle the spurious interrupts coming from the host
on an invalid channel, the channel doorbell interrupts are
disabled during initialization phase. These are enabled after
receiving the start command for a particular channel.

Change-Id: I12bb315bcd249383ed442ad969e84c9eef25a324
Signed-off-by: Abhinab Abhinab <aabhinab@codeaurora.org>
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
2021-07-02 11:51:02 -07:00
Subramanian Ananthanarayanan
ec8cdae293 msm: mhi_dev: check for error during ring processing
The change is to check for error code from cmd processing in case
of db pending cases, to avoid rd_offset increment.

Change-Id: If213297fe02ec1087bfab572f5af97b1e7bb5791
Signed-off-by: Subramanian Ananthanarayanan <skananth@codeaurora.org>
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
2021-07-02 11:51:02 -07:00
Nitesh Gupta
45edd7ec79 msm: mhi_dev: free allocated memory in reverse order of allocation
Freeing cmd_ctx before ereqs will result into NULL ptr
dereference. Freeing memory in proper order.

Change-Id: Ie999017685574e940685eee3b7c205ebe1672664
Signed-off-by: Nitesh Gupta <nitegupt@codeaurora.org>
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
2021-07-02 11:51:01 -07:00
Nitesh Gupta
e623db906d msm: mhi: Queue channel db only if channel is open
Channel interrupts are seen on device even before,
channel ring is initialized. Queuing pending work
without checking ring status can lead to processing
of spurious interrupts. Adding proper checks in place
before queuing channel doorbell.

Change-Id: I3ccd7302b535d2b8ef63eada9d7a1fe553dccdaa
Signed-off-by: Nitesh Gupta <nitegupt@codeaurora.org>
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
2021-07-02 11:51:01 -07:00
Subramanian Ananthanarayanan
ad22cfa30a msm: mhi_dev: Allocate ring element during M0
Device allocates ring memory during mmio initialization, this
causes 128 event ring elements to be created as MHICFG
register may not be updated by the host. This causes memory
to get exhausted leading to an MMIO init failure.

The Change is to allocate ring memory during M0, during which
MHICFG register is bound to be updated by the host.

Change-Id: I04a0e0ed79a46f16f96e2be4c5c68cba9ee2c99d
Signed-off-by: Subramanian Ananthanarayanan <skananth@codeaurora.org>
Signed-off-by: Gauri Joshi <gaurjosh@codeaurora.org>
2021-07-02 11:50:38 -07:00
Hemant Kumar
89d2d76a29 pci: msm: Get rid of msm pcie device table
Since pcidev_table is no longer used in the driver
get rid of the table entry from msm pcie device
structure. Also remove unused structure members
from msm_pcie_device_info. Since device table
is removed, rename msm_pcie_config_device_table
to msm_pcie_config_device_info.

Change-Id: I5359cc0f85d6b7f9f069f7decc3bc67105543abb
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
2021-07-02 06:21:44 -07:00
Hemant Kumar
e9efafa35c pci: msm: Remove RC and EP config space shadow save and restore
All endpoints and bridge are performing their config space save
and restore. Hence root complex driver does not need to perform
the same on behalf of them. For root complex use PCI framework
provided APIs to perform RC config space save and restore. Save
golden copy of the RC config space upon enumeration and use it
to restore RC config space in case of link down. Get rid of all
custom APIs for saving, restoring and dumping of RC and EP config
space entries.

Change-Id: I466e26aaaee0ae317323aae0c535c3319f95e681
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
2021-07-02 06:20:12 -07:00
Yuanfang Zhang
5de46e8161 coresight: fix etr pice mode issue
Only start the sw mode when pcie_path is configured as sw.

Change-Id: I3b9fb890008760b0a25827bb039cd378512f4efe
Signed-off-by: Yuanfang Zhang <zhangyuanfang@codeaurora.org>
2021-07-02 14:16:51 +08:00
Lei Chen
c2b3cdaad3 defconfig: sdxlemur: Enable DRM and GKI_HIDDEN_DRM_CONFIGS on sdxlemur
This change enables DRM and GKI_HIDDEN_DRM_CONFIGS for QPIC display
on sdxlemur.

Change-Id: I856d26e0dafcffd523eefc660f00612448a4529f
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
2021-07-02 13:49:37 +08:00