Commit graph

892,791 commits

Author SHA1 Message Date
Pavankumar Kondeti
dfd45fa093 sched/walt: Improve the scheduler
This change is for general scheduler improvement.

Change-Id: I616acbe5bfdb0e1bf88e923d98b4a3d54d26d942
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
2020-12-15 14:58:36 +05:30
qctecmdr
aa860b5b17 Merge "usb: f_gsi: Send zero length packet for MBIM/GPS on cable connect" 2020-12-10 16:11:03 -08:00
qctecmdr
fdf6a38b66 Merge "msm: kgsl: Properly walk the list of timeline signals in a aux command" 2020-12-10 16:11:03 -08:00
Jordan Crouse
a8e0225571 msm: kgsl: Properly walk the list of timeline signals in a aux command
Commit 36b196ce5c ("msm: kgsl: Add software timelines") didn't properly
advance the user source pointer while walking the incoming list of timeline
signals in an aux commmand which resulted in only the first listed timeline
getting signaled.

Fixes: 36b196ce5c ("msm: kgsl: Add software timelines")
Change-Id: Ic0dedbad400f276abea6b368421ccdcef1645b9e
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
2020-12-10 14:06:05 -07:00
qctecmdr
46105a7401 Merge "mtd: msm_qpic_nand: Workaround to get the correct density for JSC part" 2020-12-10 11:38:52 -08:00
qctecmdr
016be0999a Merge "Revert "scsi: ufs: Increase ah8 idle to 10ms"" 2020-12-10 11:38:51 -08:00
qctecmdr
f7390a26b1 Merge "defconfig: Enable new file encryption framework" 2020-12-10 11:38:51 -08:00
qctecmdr
3d160e50f2 Merge "iommu: arm-smmu: skip tlb flush during unmap" 2020-12-10 11:38:51 -08:00
qctecmdr
3848433c36 Merge "phy: ufs: add UFS PHY support for SM8150 platform" 2020-12-10 11:38:51 -08:00
qctecmdr
96d15d544e Merge "netfilter: x_tables: Switch synchronization to RCU" 2020-12-10 11:38:50 -08:00
qctecmdr
f16a9db54f Merge "iommu/arm-smmu: Update the implementation defined page number macros" 2020-12-10 11:38:50 -08:00
qctecmdr
1297536962 Merge "usb: dwc3: core: Destroy ipc log context on remove" 2020-12-10 06:46:25 -08:00
qctecmdr
324146f8ba Merge "mm/madvise: remove racy mm ownership check" 2020-12-10 06:46:25 -08:00
qctecmdr
4f0abb7427 Merge "dm verity: skip verity work on I/O errors when system is shutting down" 2020-12-10 06:46:25 -08:00
qctecmdr
7c3f466a36 Merge "input: qcom-hv-haptics: fix out of bound of FIFO samples array" 2020-12-10 06:46:24 -08:00
qctecmdr
37093a2edd Merge "firmware: qcom: tzbsp_diag info not required for qsee_log" 2020-12-10 06:46:24 -08:00
qctecmdr
c81a2b0920 Merge "arm64: defconfig: Enable CRYPTO_SHA1_ARM64_CE algorithm" 2020-12-10 06:46:23 -08:00
qctecmdr
3e35a068a5 Merge "msm: pcie: Disable access to PARF register when link is disabled" 2020-12-10 06:46:23 -08:00
qctecmdr
f274bc425e Merge "defconfig: msm-5.4: Adding sfe support to sdxlemur target" 2020-12-10 06:46:23 -08:00
qctecmdr
609dff6223 Merge "defconfig: Enable new file encryption framework" 2020-12-10 06:46:22 -08:00
qctecmdr
32473be6ee Merge "mmc: core: Add partial initialization support" 2020-12-10 06:46:22 -08:00
qctecmdr
2ae503d752 Merge "defconfig: Enable Novatek NT36xxx Touch for yupik target" 2020-12-10 06:46:21 -08:00
Phanindra Babu Pabba
25117d2ee0 defconfig: Enable new file encryption framework
Following flags are needed to support block crypto
based inline encryption framework on eMMC devices:

1. CONFIG_MMC_CQHCI_CRYPTO
2. CONFIG_MMC_CQHCI_CRYPTO_QTI.

Change-Id: Ic87330eaa1e95d7347a13d631bb5c0c734b92d2c
Signed-off-by: Phanindra Babu Pabba <pabba@codeaurora.org>
2020-12-10 16:19:20 +05:30
Nitin Rawat
b16f5839ec Revert "scsi: ufs: Increase ah8 idle to 10ms"
There is some power impact seen with autohibern8 idle
timer value of 10ms. Hence reverting back the autohiber8 timer
value back to 5ms.

This reverts commit ef3f24dd1c.

Change-Id: Ic2f97e6f53e1711a869c9617e15c06e53d1e2e33
Signed-off-by: Nitin Rawat <nitirawa@codeaurora.org>
2020-12-10 15:19:00 +05:30
qctecmdr
b54ec6fdfe Merge "defconfig: clean up debug config fragment for SDXLEMUR" 2020-12-09 19:47:45 -08:00
qctecmdr
712f68c376 Merge "sound: usb: Unmap secondary event ring before freeing" 2020-12-09 19:47:45 -08:00
qctecmdr
ac19da4fa6 Merge "iommu/arm-smmu: Fix io-coherency enablement for clients using S1 bypass" 2020-12-09 19:47:44 -08:00
qctecmdr
c4c415a165 Merge "msm: ipa: store eth_ready_info pointer" 2020-12-09 19:47:44 -08:00
Veera Vegivada
256d3f69e1 phy: ufs: add UFS PHY support for SM8150 platform
Add support for new UFS PHY on SM8150 platform.

Change-Id: I8d28e798c080706280e0b55bcf474c3422985d2a
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2020-12-10 08:28:28 +05:30
Prakash Gupta
c765bad7cc iommu: arm-smmu: skip tlb flush during unmap
With fragmented physical memory, mappings are generated of lower granule.
This increases the unmap latency of large buffers.  When not supporting
demand paging in smmu, unmap can defer the invalidation till next map.
This change aggregates invalidations across multiple unmaps till a new
mapping is created on that context. The new mapping can be using an iova
previously unmapped hence the stale TLB can cause issue. Hence invalidate
the TLB during map.

Change-Id: I1d64227ca075067a43075729ba26be684126d679
Signed-off-by: Prakash Gupta <guptap@codeaurora.org>
2020-12-10 01:05:08 +05:30
Isaac J. Manjarres
76296974fd iommu/arm-smmu: Fix io-coherency enablement for clients using S1 bypass
When a context bank's SCTLR is programmed for an SMMU client
that wishes to bypass S1 translations and enable io-coherency, the
SHCFG bitfield of the SCTLR is set to 0. This means that a
client's transaction's shareability memory attribute will not be
modified as it goes through the SMMU.

This is problematic if the SMMU client's transaction is marked as
non-shareable, as the attribute will not be modified to be classified
as io-coherent, since io-coherent transactions should be cacheable
and shareable. Instead, the transaction will not snoop the CPU
caches, and will go to DDR, and may read incorrect data.

Thus, program the SHCFG bitfield in the context bank's SCTLR to
override the shareability attribute to outer shareable when
enabling io-coherency for clients using S1 bypass.

Change-Id: Ia4c1bbe7812ce7c2062c636e2b1bb39fa1ac516c
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2020-12-09 10:39:00 -08:00
Subash Abhinov Kasiviswanathan
de256ffb4a netfilter: x_tables: Switch synchronization to RCU
When running concurrent iptables rules replacement with data, the per CPU
sequence count is checked after the assignment of the new information.
The sequence count is used to synchronize with the packet path without the
use of any explicit locking. If there are any packets in the packet path
using the table information, the sequence count is incremented to an odd
value and is incremented to an even after the packet process completion.

The new table value assignment is followed by a write memory barrier so
every CPU should see the latest value. If the packet path has started with
the old table information, the sequence counter will be odd and the
iptables replacement will wait till the sequence count is even prior to
freeing the old table info.

However, this assumes that the new table information assignment and the
memory barrier is actually executed prior to the counter check in the
replacement thread. If CPU decides to execute the assignment later as there
is no user of the table information prior to the sequence check, the packet
path in another CPU may use the old table information. The replacement
thread would then free the table information under it leading to a use
after free in the packet processing context-

Unable to handle kernel NULL pointer dereference at virtual
address 000000000000008e
pc : ip6t_do_table+0x5d0/0x89c
lr : ip6t_do_table+0x5b8/0x89c
ip6t_do_table+0x5d0/0x89c
ip6table_filter_hook+0x24/0x30
nf_hook_slow+0x84/0x120
ip6_input+0x74/0xe0
ip6_rcv_finish+0x7c/0x128
ipv6_rcv+0xac/0xe4
__netif_receive_skb+0x84/0x17c
process_backlog+0x15c/0x1b8
napi_poll+0x88/0x284
net_rx_action+0xbc/0x23c
__do_softirq+0x20c/0x48c

This could be fixed by forcing instruction order after the new table
information assignment or by switching to RCU for the synchronization.

Change-Id: I41ffb931b711cd2de9896d9ca7f13dda79e6709f
Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
2020-12-09 10:18:47 -08:00
Jeevan Shriram
26721bcead defconfig: clean up debug config fragment for SDXLEMUR
defconfigs generated at runtime scan through dependency order of
config fragments and enable respective config flag. Remove duplicate and
unnecessary configs in debug config fragment.

Change-Id: Ifbc74382a16479e0b7de068fe9c92211f49c1c92
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
2020-12-09 09:31:10 -08:00
Sriharsha Allenki
2933225984 usb: dwc3: core: Destroy ipc log context on remove
The IPC log context and the log buffers allocated
are not destroyed upon remove, this will lead to
memory leak and cause memory allocation failures,
if the probe fails indefinitely.

Change-Id: I6844507cb5c5bec4908f34b3f00090594d2cefcf
Signed-off-by: Sriharsha Allenki <sallenki@codeaurora.org>
2020-12-09 08:14:11 -08:00
qctecmdr
323f338f25 Merge "interconnect: qcom: Add OSM L3 support on SM8150" 2020-12-09 07:54:25 -08:00
qctecmdr
fada40633a Merge "msm: ipa3: add support on sockv5 info" 2020-12-09 07:54:25 -08:00
qctecmdr
0849eb81df Merge "f2fs: change to use rwsem for cp_mutex" 2020-12-09 07:54:25 -08:00
qctecmdr
1e1b65a360 Merge "power: supply: qti_battery_charger: Add TIME_TO_FULL_NOW property" 2020-12-09 07:54:24 -08:00
qctecmdr
c337ef1596 Merge "scsi: ufs-qcom: update phy revision information" 2020-12-09 07:54:24 -08:00
qctecmdr
db33e6b422 Merge "defconfig: gen3auto: Enable SPMI PMIC drivers" 2020-12-09 07:54:23 -08:00
qctecmdr
c223f4f164 Merge "power: qti_battery_charger: Add a shutdown notification" 2020-12-09 07:54:22 -08:00
Sarthak Garg
8d65c90a8a mtd: msm_qpic_nand: Workaround to get the correct density for JSC part
The 8 x 8 JSC MCP part has 2 x 4Gbit NAND dies from Hynyx and
supports ONFI. But ONFI parameter page field values below read from the
device only account for 4Gbit instead of 8Gbit:

Pages/Block : 64
Page size  : 4096
num_blocks_per_unit : 2048
num_units : 1

JSC vendor has no plans to “correct” the ONFI parameter page
field values in their current and future 8 x 8 MCP parts to properly
identify the NAND device size as 8Gbit.

Using Read ID values (manufacture ID (0xAD), device ID(0xA3)) instead to
identify the part and multiplying the density to identify the part as
8Gbit device size.

Change-Id: Id900f3475e68740597fbc4e6decb1b7920f09c57
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
2020-12-09 14:23:50 +05:30
Vaibhav Agrawal
62549fc9c2 defconfig: Enable new file encryption framework
Following flags are needed to support block crypto
based inline encryption framework on EMCC devices:
1. CONFIG_MMC_CQHCI_CRYPTO.
2. CONFIG_MMC_CQHCI_CRYPTO_QTI.

Test:
1. Device booted upto UI with File Based Encryption enabled.
2. Key insertion using fscryptctl tool.
3. Created new files under /data and checked retention across
   multiple re-boots.
4. vts_kernel_encryption_test tests.
5. check_encryption test for verifying metadata encryption.

Change-Id: I574838b0e65e336d2c056ab7cfce8c9cd3e801e0
Signed-off-by: Vaibhav Agrawal <vagrawa@codeaurora.org>
2020-12-09 00:27:07 -08:00
qctecmdr
aa01bdf5fa Merge "pci: msm: Dump PCIe registers upon WAKE assertion" 2020-12-08 23:22:30 -08:00
qctecmdr
80b988c32b Merge "dt-bindings: iio: Add ADC support for PM7325 and PM7325B" 2020-12-08 23:22:30 -08:00
qctecmdr
5dbc56a5fc Merge "arm64: defconfig: Add mproc related defconfig for sa8155" 2020-12-08 23:22:30 -08:00
qctecmdr
879422d564 Merge "power: smb1355: Extend minoff-time and dead-time for SMB1355" 2020-12-08 23:22:29 -08:00
Amir Levy
a0fe172a68 msm: ipa: store eth_ready_info pointer
store eth_ready_info pointer for late callback
trigger instead of storing cb and user data addresses.
eth_ready_info pointer is static and shall be searched
when callback is unregistered.

Change-Id: I03cbbc4920ee663890bad12ece6d41e9bd2a68d5
Signed-off-by: Amir Levy <alevy@codeaurora.org>
2020-12-09 09:21:37 +02:00
Sachin Grover
e1cf010956 arm64: defconfig: Enable CRYPTO_SHA1_ARM64_CE algorithm
This is to enable SHA-1 digest algorithm (ARMv8 Crypto Extensions).

Change-Id: Ic6d428907debb0dcd065a72537f4acf4a70f1e6b
Signed-off-by: Sachin Grover <sgrover@codeaurora.org>
2020-12-08 23:13:54 -08:00
Minchan Kim
475c63f782 mm/madvise: remove racy mm ownership check
Jann spotted the security hole due to race of mm ownership check.

If the task is sharing the mm_struct but goes through execve() before
mm_access(), it could skip process_madvise_behavior_valid check.  That
makes *any advice hint* to reach into the remote process.

This patch removes the mm ownership check.  With it, it will lose the
ability that local process could give *any* advice hint with vector
interface for some reason (e.g., performance).  Since there is no
concrete example in upstream yet, it would be better to remove the
abiliity at this moment and need to review when such new advice comes
up.

Change-Id: I536de5167b6cf7378a06a6b7815f1dd2869a56a4
Fixes: ecb8ac8b1f14 ("mm/madvise: introduce process_madvise() syscall: an external memory hinting API")
Reported-by: Jann Horn <jannh@google.com>
Suggested-by: Jann Horn <jannh@google.com>
Signed-off-by: Minchan Kim <minchan@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Git-Commit: a68a0262abdaa251e12c53715f48e698a18ef402
Git-Repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Charan Teja Reddy <charante@codeaurora.org>
2020-12-09 12:31:23 +05:30