Commit graph

893,196 commits

Author SHA1 Message Date
Kiran Gunda
e69e8b1b39 leds: qpnp-flash-v2: Fix out-of-bound array access
Fix out-of-bound array access by using the right
offset-mask in getting the OTST status.

Change-Id: I89a4176251ea9157c5dd997b3c11bfcb07420a4f
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
2020-12-30 19:54:50 -08:00
qctecmdr
b22b60a089 Merge "clk: qcom: debugcc: Add support for CPU clock measure for SDXNIGHTJAR" 2020-12-30 06:11:58 -08:00
qctecmdr
bc6a760dd4 Merge "arm64: defconfig: enable cma debugfs" 2020-12-30 06:11:58 -08:00
qctecmdr
fd3064d1d5 Merge "defconfig: gen3auto: Enable arm smmu driver for gen3auto" 2020-12-30 06:11:58 -08:00
qctecmdr
afff9567ed Merge "clk: qcom: clk-alpha-pll: Replace hw->init in PLL code" 2020-12-30 06:11:58 -08:00
qctecmdr
414ed94edd Merge "defconfig: sdxlemur: Enable R8125 driver" 2020-12-30 06:11:57 -08:00
qctecmdr
8cd8f78e23 Merge "arm64: defconfig: Add support for CAMCC for YUPIK" 2020-12-30 06:11:57 -08:00
qctecmdr
53cbc770ba Merge "cnss2: Add new API to get QMI related timeouts" 2020-12-30 01:29:22 -08:00
qctecmdr
b31e09bdd8 Merge "cnss2: Kconfig: Add CONFIG_CNSS_WCN7850 flag" 2020-12-30 01:29:21 -08:00
qctecmdr
ed275f783d Merge "defconfig: Enable icnss2 config for Yupik" 2020-12-30 01:29:21 -08:00
qctecmdr
afaf0dd0ad Merge "i2c-msm-geni: Initialize completion variable before txfer request" 2020-12-30 01:29:21 -08:00
qctecmdr
ab416fc7c2 Merge "coresight: Add snapshot of Coresight Fuse driver" 2020-12-30 01:29:20 -08:00
qctecmdr
3572600b5b Merge "usb: dwc3-msm: Add support for snps SSPHY suspend in system suspend" 2020-12-30 01:29:20 -08:00
qctecmdr
ceec7e5038 Merge "msm: adsprpc: Copy correct size for async job" 2020-12-30 01:29:20 -08:00
qctecmdr
5183288436 Merge "defconfig: Enable SOCINFO config for sdxnightjar target" 2020-12-29 19:19:54 -08:00
qctecmdr
617a6ca32e Merge "drivers: lpm-levels: Return correct value while suspend" 2020-12-29 19:19:53 -08:00
qctecmdr
1bbfb84274 Merge "Merge android11-5.4.61+ (e0b1644) into msm-5.4" 2020-12-29 19:19:53 -08:00
qctecmdr
1ac401219b Merge "interconnect: qcom: Add OSM L3 support on SCSHRIKE" 2020-12-29 19:19:53 -08:00
qctecmdr
629b150b59 Merge "icnss2: Clear SMP2P data during SSR" 2020-12-29 19:19:52 -08:00
qctecmdr
d6c74bdc8a Merge "usb: f_gsi: Increase GPS EP maxpacket size to 64bytes" 2020-12-29 19:19:52 -08:00
qctecmdr
ddd209806d Merge "usb: f_gsi: Disable function remote wake-up capability for DPL" 2020-12-29 19:19:52 -08:00
qctecmdr
aeffceb7f7 Merge "cnss2: Add config to disable time sync feature" 2020-12-29 19:19:51 -08:00
qctecmdr
d8a0d0db56 Merge "cnss2: Use proper DMA mask based on device ID" 2020-12-29 19:19:51 -08:00
Karthik Rudrapatna
b74c0a27e6 defconfig: sdxlemur: Enable R8125 driver
Enable R8125 driver.

Change-Id: I28b13e22c22822e5e2baa7f6c2e623a57b187d2e
Acked-by: Lakshit Tyagi <ltyagi@codeaurora.org>
Signed-off-by: Karthik Rudrapatna <krudrapa@codeaurora.org>
2020-12-28 10:28:30 -08:00
Taniya Das
d7293b4f0e clk: qcom: clk-alpha-pll: Replace hw->init in PLL code
The hw->init is no longer valid after the HW clock is registered with
the clock framework, thus clean up the clock enable/disable. While at it
update the list register offset.

Change-Id: I965cd1d5c14efd2bea8cc220f2b19ed1f3ddfb8c
Signed-off-by: Taniya Das <tdas@codeaurora.org>
2020-12-28 17:02:53 +05:30
Taniya Das
456857a0ef clk: qcom: clk-regmap: Add support for devm_clk_regmap_list_node
There can be cases where the clock providers have multiple regmaps and
directly registers to the clock framework. The clk regmap ops like list
registers/clk rate max would be registered only if the provider is added
to the regmap list node.
Thus expose this API for those providers to add to the list.

Change-Id: I1463c12eeed431d30e96404f2162dd75d202d4b9
Signed-off-by: Taniya Das <tdas@codeaurora.org>
2020-12-28 17:02:02 +05:30
Saurabh Ambulkar
55611bbd81 defconfig: gen3auto: Enable arm smmu driver for gen3auto
Enable arm smmu driver so that clients can use.

Change-Id: Ia1838b2d97e95c5fe224f735e42ce3e5bdbf008a
Signed-off-by: Saurabh Ambulkar <sambulka@codeaurora.org>
2020-12-28 16:21:34 +05:30
Rakesh Kota
133892d48d clk: qcom: debugcc: Add support for CPU clock measure for SDXNIGHTJAR
Add support for debug clock controller to measure
frequency of APCS mux clock.

Change-Id: I951c420c52aa62eb6a3cbfc0ccea9d244de6bb06
Signed-off-by: Rakesh Kota <kotarake@codeaurora.org>
2020-12-28 15:33:48 +05:30
Jeya R
593398e786 msm: adsprpc: Copy correct size for async job
Copy correct size in invoke2 for async job to avoid
stack out-of-bounds issue.

Change-Id: Ia4ba5acf372ef46ab89b860c7d9ce47f49a9672e
Acked-by: Deepika Singh <dsi@qti.qualcomm.com>
Signed-off-by: Jeya R <jeyr@codeaurora.org>
2020-12-28 14:14:14 +05:30
Ajay Agarwal
b595281eb8 usb: dwc3-msm: Add support for snps SSPHY suspend in system suspend
Currently the platforms using SNPS SSPHY do not suspend it so as
to receive SS wakeup events via pwr_event_irq. But certain
telematics platforms do not need SS wakeup in system suspend
scenario.
USB wakeup from PM suspend/hibernation is not a requirement for
automotive/telematics platforms. Use enable_wakeup parameter in
dwc3_msm_suspend call to allow SSPHY suspend to happen and also
to keep the IRQs enabled/disabled.

Change-Id: I691585e15539490e63a345fe2b3aacf182352399
Signed-off-by: Ajay Agarwal <ajaya@codeaurora.org>
Signed-off-by: Harsh Agarwal <harshq@codeaurora.org>
2020-12-27 22:38:08 -08:00
Ajay Agarwal
74b8a97e90 usb: host: Modify PM handling for USB interconnect platforms
Currently the PM handling power collapses the core and issues
reset-resume for all the connected devices, both during system
suspend-resume and hibernation-restore scenarios. But certain USB
interconnect platforms want the connected device to not undergo
reset-resume on system resume.
Modify the operations to keep the core powered up, PHY resources
ON and xhci_resume with hibernated flag as 'false' so that
suspend-resume of the connected device is done on resume from
system suspend. Keep the hibernation operation as is.
Also change the DT flag to 'qcom,ignore-wakeup-src-in-hostmode'.

Change-Id: I661494595a3e270890174e0952a67985db58706d
Signed-off-by: Ajay Agarwal <ajaya@codeaurora.org>
Signed-off-by: Harsh Agarwal <harshq@codeaurora.org>
2020-12-27 22:37:29 -08:00
qctecmdr
5bf38f9905 Merge "icc: dt-bindings: add endpoint IDs for interconnects for MONACO" 2020-12-27 17:54:23 -08:00
qctecmdr
502034be7b Merge "msm: pci: use local pointer for rpmsg_device while sending rpmsg" 2020-12-27 17:54:22 -08:00
qctecmdr
c75c3d980f Merge "usb: misc: nb7vpq904m: fix suspend/resume issue" 2020-12-27 17:54:22 -08:00
Naman Padhiar
bf935090f4 icnss2: Clear SMP2P data during SSR
Clear smp2p data during subsystem down to
prevent false smp2p notification to FW when
subsystem is up.

Change-Id: Iaa9a360e27a6e59d34ba9f02a28ce5dcf71ed0f5
Signed-off-by: Naman Padhiar <npadhiar@codeaurora.org>
2020-12-24 20:19:23 -08:00
Chandana Kishori Chiluveru
87f4d33019 usb: f_gsi: Increase GPS EP maxpacket size to 64bytes
Currently usb driver is using 8 bytes request on interrupt endpoint
for all CDC functions. GPS host driver is expecting short packet/zero
length packet on interrupt endpoint and failing the transfer with 8 bytes
maxpacket. Increase the maxpacket size to 64 bytes so that host ends
the transfer with a short packet.

Change-Id: Icc9919fbd633468d3cc7d4d8ab1945730cdc7c06
Signed-off-by: Chandana Kishori Chiluveru <cchiluve@codeaurora.org>
2020-12-24 04:55:31 -08:00
Odelu Kukatla
299903dad6 icc: dt-bindings: add endpoint IDs for interconnects for MONACO
Add master and slave IDs for all Qualcomm Technologies, Inc. Monaco
interconnect providers which consumers can use to set bandwidth
constraints and find paths in the NoC (Network-On-Chip) topology.

Change-Id: Id2e816a74e382946c02345a5d1e39ed1d913ef90
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
2020-12-24 15:33:03 +05:30
qctecmdr
28255001cf Merge "spi: spi-msm-geni: Propagate missing change from 4.14 to 5.4" 2020-12-23 23:10:16 -08:00
qctecmdr
959b3a1fac Merge "msm: kgsl: Add apb_pclk to the clock list and increase KGSL_MAX_CLKS" 2020-12-23 23:10:16 -08:00
qctecmdr
a7f770af3b Merge "arm: defconfig: Enable interconnect driver for NIGHTJAR" 2020-12-23 23:10:15 -08:00
qctecmdr
475b0d24b7 Merge "usb: gsi: Allow suspend upon previous suspend failure in gsi_suspend" 2020-12-23 23:10:15 -08:00
qctecmdr
44abfd814c Merge "input: touchscreen: Enable Novatek nt36xxx Module" 2020-12-23 23:10:15 -08:00
Lijuan Gao
daae44ea12 defconfig: Enable SOCINFO config for sdxnightjar target
Enable SOCINFO config for sdxnightjar soc_id query.

Change-Id: Iaa59d03e3454d2d4278775ed4d89d13d71e9b65b
Signed-off-by: Lijuan Gao <lijuang@codeaurora.org>
2020-12-24 14:25:17 +08:00
Tushar Nimkar
019a94d233 drivers: lpm-levels: Return correct value while suspend
Currently lpm_suspend_enter and lpm_cpuidle_s2idle return
success always. This misleads on succcess and failure counts.

This change adds support to return correct value to caller.

Change-Id: I57dd0a4385f16f0e0aa1c92d602c0816ed358e2c
Signed-off-by: Tushar Nimkar <tnimkar@codeaurora.org>
2020-12-24 10:33:39 +05:30
Veera Vegivada
3dde3cb49e interconnect: qcom: Add OSM L3 support on SCSHRIKE
Add Operating State Manager (OSM) L3 interconnect provider support on
SCSHRIKE SoCs.

Change-Id: I69bd044422520601b121f260ff0cebf07d5a5220
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2020-12-24 09:49:44 +05:30
Veera Vegivada
c680e4f46f interconnect: qcom: Refractor OSM L3 code
Refractor the OSM L3 driver to make it easy to extend for
other targets.

Change-Id: Id9e9ff3c2e9a299fcee8881c68f43649b866259b
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2020-12-24 09:49:06 +05:30
Veera Vegivada
21b7e009d6 interconnect: qcom: Add SCSHRIKE interconnect provider driver
Introduce QTI SCSHRIKE specific provider driver using the
interconnect framework.

Change-Id: I16865c527a4e70d2e0e42f048bfa451a31027462
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2020-12-24 09:46:57 +05:30
Nitesh Gupta
5fc6f0eef5 arm64: defconfig: Adding all CoreTech Defconfigs to Mainline 5.4
Changes Included:-
1.) PCIE:- 3172299 3197640
2.) USB:- 3186918 3325023
3.) BUSES:- 3198026
4.) STORAGE:- 3261577.

Change-Id: I69c4cded2463d78b31302673114f462fe4e88461
Signed-off-by: Nitesh Gupta <nitegupt@codeaurora.org>
2020-12-23 19:45:36 -08:00
Manu Gautam
3717aafa04 usb: f_gsi: Fix GSI enable logic for ADPL only composition
Driver enables GSI wrapper only if OUT EP is present in
GSI interface which is not the case with DPL function.
This logic works as long as there is another GSI function
present with OUT EP (e.g. RMNET/RNDIS). However, if ADPL is
the only GSI function in composition then driver does all
the EP specific programming in USB GSI wrapper but doesn't
enable it. Since, initial doorbell is rung by software, data
transfer does start but eventually stall happens as USB GSI
wrapper doesn't ring doorbell.
Fix it by not having an EP check while enabling GSI.

Change-Id: Ia40209d5a3f3b5947b13e8909ef9f994200f7a85
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
2020-12-23 08:52:39 -08:00
Mukesh Kumar Savaliya
20e81ac78a i2c-msm-geni: Initialize completion variable before txfer request
During I2C GSI mode transfer scenario, there is a potential race between
initializing the completion variable and waiting for the completion.
After submitting the DMA transfer request, initializing the completion
may actually reset the received event as DMA could have complete the
transfer immediately before driver waits for the event. Then it can
never receive the completion and results in timeout.

This change initializes the completion variable before submitting the
DMA transfer request and then waits for the completion.

Change-Id: I537d1187a84171a0811862efd5e118c8d8b57fef
Signed-off-by: Mukesh Kumar Savaliya <msavaliy@codeaurora.org>
2020-12-23 22:12:44 +05:30