mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-08 11:45:53 -05:00
77fa5c31ca
This change adds refclock base address and sets the clock scheme to cml. Also make major_rev of the phy to 1 and disable susphy for controller during phy initialization as recommended in controller data book. Change-Id: Idb293c7fe67c0c37ec85f7807ba487685af2a461
241 lines
6 KiB
Devicetree
241 lines
6 KiB
Devicetree
&soc {
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usb3: ssusb@8a00000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x08a00000 0xf8c00>,
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<0x0007e000 0x400>;
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reg-names = "core_base", "ahb2phy_base";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts-extended = <&intc GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
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<&wakegic 54 IRQ_TYPE_LEVEL_HIGH>,
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<&wakegic 49 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwr_event_irq","ss_phy_irq", "hs_phy_irq";
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USB3_GDSC-supply = <&gdsc_usb30>;
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qcom,lpm-to-suspend-delay-ms = <2000>;
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clocks = <&gcc GCC_USB30_MASTER_CLK>,
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<&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
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<&gcc GCC_USB30_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_SLEEP_CLK>,
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<&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&gcc GCC_USB_PHY_CFG_AHB_CLK>;
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clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",
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"xo", "cfg_ahb_clk";
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resets = <&gcc GCC_USB_30_BCR>;
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reset-names = "core_reset";
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qcom,core-clk-rate = <120000000>;
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interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
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interconnects = <&system_noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
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<&system_noc MASTER_USB3 &pc_noc SLAVE_IPA_CFG>,
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<&bimc MASTER_AMPSS_M0 &system_noc SLAVE_USB3>;
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qcom,interconnect-values-nom = /* NOMINAL Votes */
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<0 680000>,
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<0 2400>,
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<0 40000>;
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qcom,interconnect-values-svs = /* SVS Votes */
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<0 680000>,
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<0 2400>,
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<0 40000>;
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qcom,num-gsi-evt-buffs = <0x3>;
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qcom,gsi-reg-offset =
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<0x0fc /* GSI_GENERAL_CFG */
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0x110 /* GSI_DBL_ADDR_L */
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0x120 /* GSI_DBL_ADDR_H */
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0x130 /* GSI_RING_BASE_ADDR_L */
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0x140 /* GSI_RING_BASE_ADDR_H */
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0x1a4>; /* GSI_IF_STS */
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qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
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dwc3@8a00000 {
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compatible = "snps,dwc3";
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reg = <0x08a00000 0xcd00>;
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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usb-phy = <&qusb_phy>, <&ssphy>;
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linux,sysdev_is_parent;
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tx-fifo-resize;
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snps,is-utmi-l1-suspend;
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snps,hird-threshold = /bits/ 8 <0x0>;
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snps,bus-suspend-enable;
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snps,usb2-gadget-lpm-disable;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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snps,dis_u2_susphy_quirk;
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xhci-imod-value = <4000>;
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maximum-speed = "super-speed";
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dr_mode = "otg";
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};
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qcom,usbbam@0x8B04000 {
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compatible = "qcom,usb-bam-msm";
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reg = <0x8b04000 0x1b000>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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qcom,usb-bam-fifo-baseaddr = <0x08604000>;
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qcom,usb-bam-num-pipes = <1>;
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qcom,disable-clk-gating;
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qcom,usb-bam-override-threshold = <0x4001>;
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qcom,usb-bam-max-mbps-highspeed = <400>;
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qcom,usb-bam-max-mbps-superspeed = <3600>;
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qcom,reset-bam-on-connect;
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qcom,pipe0 {
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label = "ssusb-qdss-in-0";
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qcom,usb-bam-mem-type = <2>;
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qcom,dir = <1>;
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qcom,pipe-num = <0>;
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qcom,peer-bam = <0>;
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qcom,peer-bam-physical-address = <0x00884000>;
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qcom,src-bam-pipe-index = <0>;
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qcom,dst-bam-pipe-index = <2>;
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qcom,data-fifo-offset = <0x0>;
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qcom,data-fifo-size = <0xc00>;
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qcom,descriptor-fifo-offset = <0xc00>;
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qcom,descriptor-fifo-size = <0x400>;
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};
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};
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};
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qusb_phy: qusb@79000 {
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compatible = "qcom,qusb2phy";
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reg = <0x00079000 0x180>,
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<0x01841030 0x4>;
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reg-names = "qusb_phy_base",
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"ref_clk_addr";
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vdd-supply = <&pmd9650_l4>;
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vdda18-supply = <&pmd9650_l5>;
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vdda33-supply = <&pmd9650_l10>;
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qcom,vdd-voltage-level = <0 928000 928000>;
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qcom,qusb-phy-init-seq = <0xf8 0x80
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0xb3 0x84
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0x83 0x88
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0xc0 0x8c
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0x30 0x08
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0x79 0x0c
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0x21 0x10
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0x14 0x9c
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0x9f 0x1c
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0x00 0x18>;
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phy_type = "utmi";
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qcom,phy-clk-scheme = "cml";
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qcom,major-rev = <1>;
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USB3_GDSC-supply = <&gdsc_usb30>;
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qcom,secure-level-shifter;
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clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
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<&gcc GCC_QUSB_REF_CLK>,
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<&gcc GCC_USB_PHY_CFG_AHB_CLK>,
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<&gcc GCC_SYS_NOC_USB3_AXI_CLK>;
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clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk",
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"iface_clk";
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resets = <&gcc GCC_QUSB2A_PHY_BCR>;
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reset-names = "phy_reset";
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};
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ssphy: ssphy@78000 {
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compatible = "qcom,usb-ssphy-qmp";
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reg = <0x00078000 0x9f8>,
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<0x01947244 0x4>;
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reg-names = "qmp_phy_base",
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"vls_clamp_reg";
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qcom,qmp-phy-init-seq = <0xac 0x14 0x00
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0x34 0x08 0x00
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0x174 0x30 0x00
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0x70 0x0f 0x00
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0x19c 0x01 0x00
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0x178 0x00 0x00
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0x194 0x06 0x3e8
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0x48 0x0f 0x00
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0x3c 0x02 0x00
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0xd0 0x82 0x00
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0xdc 0x55 0x00
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0xe0 0x55 0x00
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0xe4 0x03 0x00
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0x78 0x0b 0x00
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0x84 0x16 0x00
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0x90 0x28 0x00
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0x108 0x80 0x00
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0x4c 0x15 0x00
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0x50 0x34 0x00
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0x54 0x00 0x00
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0x18c 0x00 0x00
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0xcc 0x00 0x00
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0x128 0x00 0x00
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0x0c 0x0a 0x00
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0x10 0x01 0x00
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0x1c 0x31 0x00
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0x20 0x01 0x00
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0x14 0x00 0x00
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0x18 0x00 0x00
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0x24 0xde 0x00
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0x28 0x07 0x00
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0x41c 0x06 0x00
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0x4d8 0x02 0x00
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0x4dc 0x4c 0x00
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0x4e0 0xb8 0x00
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0x508 0x77 0x00
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0x50c 0x80 0x00
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0x514 0x03 0x00
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0x51c 0x16 0x00
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0x510 0x0c 0x00
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0x268 0x45 0x00
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0x2ac 0x12 0x00
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0x294 0x06 0x00
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0x824 0x15 0x00
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0x828 0x0e 0x00
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0x8c8 0x83 0x00
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0x8c4 0x02 0x00
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0x8cc 0x09 0x00
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0x8d0 0xa2 0x00
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0x8d4 0x85 0x00
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0x880 0xd1 0x00
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0x884 0x1f 0x00
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0x888 0x47 0x00
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0x864 0x1b 0x00
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0x8b8 0x75 0x00
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0x8bc 0x13 0x00
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0x8b0 0x86 0x00
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0x8a0 0x04 0x00
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0x88c 0x44 0x00
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0x870 0xe7 0x00
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0x874 0x03 0x00
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0x878 0x40 0x00
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0x87c 0x00 0x00
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0x9d8 0x88 0x00
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0xffffffff 0xffffffff 0x00>;
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qcom,qmp-phy-reg-offset = <0x974 0x8d8 0x8dc 0x804 0x800
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0x808>;
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vdd-supply = <&pmd9650_l4>;
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core-supply = <&pmd9650_l5>;
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qcom,vdd-voltage-level = <0 928000 928000>;
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qcom,core-voltage-level = <0 1800000 1800000>;
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clocks = <&gcc GCC_USB3_AUX_CLK>,
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<&gcc GCC_USB3_PIPE_CLK>,
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<&gcc GCC_USB_PHY_CFG_AHB_CLK>,
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<&rpmcc RPM_SMD_LN_BB_CLK>,
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<&gcc GCC_USB_SS_REF_CLK>;
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clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk",
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"ref_clk_src", "ref_clk";
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resets = <&gcc GCC_USB3_PHY_BCR>,
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<&gcc GCC_USB3PHY_PHY_BCR>;
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reset-names = "phy_reset", "phy_phy_reset";
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};
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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};
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