A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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Merge "ARM: dts: msm: Add LLCC for sdxlemur"

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qctecmdr 2020-08-28 10:46:00 -07:00 • committed by Gerrit - the friendly Code Review server
commit 8d99ec0c1e
2 changed files with 10 additions and 1 deletions
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2
bindings/arm/msm/qcom,llcc.txt
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@ -12,7 +12,7 @@ Properties:
Usage: required
Value type: <string>
Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc"
or "qcom,shima-llcc".
or "qcom,shima-llcc" or "qcom,sdxlemur-llcc"
"qcom,llcc-v2" must be appended for V2 hardware.
- reg:

9
qcom/sdxlemur.dtsi
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@ -458,6 +458,15 @@
#hwlock-cells = <1>;
};
cache-controller@9200000 {
compatible = "qcom,sdxlemur-llcc", "qcom,llcc-v2";
reg = <0x9200000 0x50000>;
reg-names = "llcc_base";
cap-based-alloc-and-pwr-collapse;
clocks = <&aopcc QDSS_CLK>;
clock-names = "aopcc_closks";
};
smem: qcom,smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;