Commit graph

879,585 commits

Author SHA1 Message Date
Raghavendra Rao Ananta
01acbed66c haven: hh_msgq: Let clients manage the buffers for hh_msgq_send
Currently, the clients of the hh_msgq driver would allocate buffers,
fill with data and call hh_msgq_send(). Upon success, hh_msgq_send()
would be freeing the buffer, while in the case of failure, the clients
are responsible for it. However, this approach of buffer management is
not symmetric and could be confusing for the clients. Hence, let the
clients take full ownership of the buffers- allocating and freeing.

Also make changes to the affected client drivers.

Change-Id: I73101d823f9d3de16414e444fde494222f584e53
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
2020-04-01 22:37:48 -07:00
Raghavendra Rao Ananta
3aa6a08878 haven: msgq: Make the send/recv wait if the cap-id is not ready
It's a highly likely situation that the clients call hh_msgq_recv()
from a thread in a polling fashion, and these threads are spawned
during client driver's initialization. Hence, it's possible that
the cap-ids for the message queues will not be ready so early and
the clients would end up continuously spinning on hh_msgq_recv(),
receiving the error -EAGAIN. To avoid this situation, put the
client process onto a wait-queue until the cap-ids are ready.

Although a little unlikely, to satisfy the symmetry, add the same
provision for the callers of hh_msgq_send() as well.

Change-Id: I4e042215c5e43271d566340ce1ef9c52ecafeb5c
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
2020-04-01 22:37:46 -07:00
Raghavendra Rao Ananta
eb5a78719a haven: Convert the cap entry locks to spinlocks
There's a potential chance that the clients can request to
send or receive the data from an interrupt context. Hence,
convert the cap_entry_lock from mutex to a spinlock.

Change-Id: Ic314a32f7a8007308c0a397e0cc44f16441c58d4
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
2020-03-30 12:19:00 -07:00
qctecmdr
1264c046de Merge "sched: walt: Improve the Scheduler" 2020-03-30 07:21:11 -07:00
qctecmdr
5ab3549e29 Merge "arm64: defconfig: Add support for LKDTM on Lahaina" 2020-03-30 07:21:11 -07:00
qctecmdr
237a73f401 Merge "msm: ipa4: new qmap flow control pipe definitions" 2020-03-30 07:21:10 -07:00
qctecmdr
c592caba4a Merge "haven: msgq: Initialize the cap-id with U64_MAX" 2020-03-30 07:21:10 -07:00
qctecmdr
51b24ffda1 Merge "msm: kgsl: Scale hub clock to 150 Mhz" 2020-03-30 07:21:10 -07:00
qctecmdr
026e011961 Merge "coresight: Add spin_lock_init for funnel and replicator" 2020-03-30 07:21:10 -07:00
qctecmdr
fd77bb96cc Merge "cnss2: Make sure PCIe link is in L0 state before updating time sync" 2020-03-29 21:21:57 -07:00
qctecmdr
9da0a58535 Merge "staging: ion: Allow for attach and detach ops to be overridden" 2020-03-29 21:21:56 -07:00
qctecmdr
47ab010aef Merge "pinctrl: qcom: Add GPIO wakeup interrupt map for Shima" 2020-03-29 21:21:56 -07:00
Raghavendra Rao Ananta
1bdf8b9d3e haven: msgq: Initialize the cap-id with U64_MAX
Currently, the cap-id for Tx and Rx of the message-queue are
initialized with 0. However, 0 is a valid value for cap-id.
A better value to initialize the cap-id is with U64_MAX. Hence,
make corrections to use U64_MAX, defined as HH_CAPID_INVAL, in
the message-queue driver.

Change-Id: Ia501e87dc3cb8d880ea3d35ff000ca07b64aeced
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
2020-03-29 13:00:48 -07:00
qctecmdr
3df7f60dd2 Merge "msm: kgsl: Don't send same bus vote repeatedly" 2020-03-29 00:33:17 -07:00
qctecmdr
e96549e852 Merge "HID: qvr: Removing axis orientation" 2020-03-29 00:33:16 -07:00
qctecmdr
3a1a6e84ba Merge "FROMGIT: driver core: Call sync_state() even if supplier has no consumers" 2020-03-29 00:33:16 -07:00
qctecmdr
1affd44480 Merge "coresight: cti: Correct checking return value of device resume" 2020-03-29 00:33:16 -07:00
qctecmdr
834d2b560e Merge "msm: adsprpc: Adding inrout buffer cache maintenance support" 2020-03-28 12:42:23 -07:00
qctecmdr
a6e75c3ac2 Merge "mhi: cntrl: qcom: notify DRV suspend if device wake is set" 2020-03-28 12:42:22 -07:00
qctecmdr
d84e7b7049 Merge "mhi: core: Add range check for channel id received in event ring" 2020-03-28 12:42:22 -07:00
qctecmdr
ed86236edb Merge "power: supply: qti_battery_charger: Allow ICL to be set only for SDP" 2020-03-28 12:42:22 -07:00
qctecmdr
d711937055 Merge "arm64: defconfig: Enable hung tasks detection" 2020-03-28 07:28:13 -07:00
qctecmdr
9d40a272d9 Merge "drivers: input: touchscreen: defer probe if panel not found" 2020-03-28 07:28:13 -07:00
qctecmdr
cf92dce455 Merge "regulator: qpnp-lcdb: Replace revid checks with DT compatible properties" 2020-03-28 07:28:13 -07:00
qctecmdr
a9f7a23680 Merge "msm: pcie: skip memory access when collecting PCIe PARF registers" 2020-03-28 07:28:12 -07:00
qctecmdr
672df0d169 Merge "defconfig: Enable mem_dump driver on gki build for lahaina" 2020-03-28 07:28:11 -07:00
Mao Jinlong
2966cf8c26 coresight: Add spin_lock_init for funnel and replicator
Add spin_lock_init for funnel and replicator to avoid spinlock issue.

Change-Id: I6cb14bfd363e8d92070af2e0e99e60eaf45d923b
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
2020-03-28 10:26:50 +08:00
Yue Ma
b29497153c cnss2: Make sure PCIe link is in L0 state before updating time sync
Current driver will check PCIe link status by reading PCIe config space
before updating time sync registers. However, there is a drawback to use
PCIe API pci_read_config_word() to access config space since it will
disable interrupt and then perform read. If PCIe link is in L1 or L1ss
state, there may be more than 4ms needed to change the link state to L0
in order to access so it will cause jank for other time critical tasks.
Hence make sure PCIe link is in L0 state before updating time sync
registers instead of checking config space.

Change-Id: I59ca63c38b5af9e38e5a04d8e679f4dfde294746
Signed-off-by: Yue Ma <yuem@codeaurora.org>
2020-03-27 17:21:04 -07:00
qctecmdr
303048eeb5 Merge "msm: cvp: A fix of cvp issue in camera" 2020-03-27 12:03:31 -07:00
Mayank Rana
93be488bb0 arm64: defconfig: Enable media and UVC drivers on Lahaina
Media and USB Video Class drivers are needed to get USB video
devices functional in USB host mode. Hence enable media and USB
video class drivers on Lahaina.

Change-Id: I70ccc146b55a564b4408496a54b044d52cbf9e41
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
2020-03-27 08:53:16 -07:00
qctecmdr
e51f74d2f1 Merge "msm: kgsl: LPAC is using incorrect pagetable" 2020-03-27 03:47:19 -07:00
qctecmdr
3415d08a46 Merge "clk: qcom: gdsc-regulator: Remove regulator voltage level voting" 2020-03-27 03:47:18 -07:00
qctecmdr
b0205cb659 Merge "interconnect: qcom: Don't vote using unrelated voters in sync_state" 2020-03-27 03:47:18 -07:00
qctecmdr
b4b4118009 Merge "scsi: ufs-qti: Enable block layer runtime PM for well-known logical units" 2020-03-27 03:47:18 -07:00
qctecmdr
c4e3acfb92 Merge "defconfig: Support for QTI inline encryption" 2020-03-27 03:47:17 -07:00
qctecmdr
61c0784673 Merge "mhi: core: move non-essential errors to log messages" 2020-03-27 03:47:17 -07:00
qctecmdr
f2aa99b14e Merge "defconfig: arm64: Enable EUD driver for GKI" 2020-03-27 03:47:17 -07:00
Mohammed Nayeem Ur Rahman
2973e84157 msm: adsprpc: Adding inrout buffer cache maintenance support
Adding inrout buffer CMO support with new cache flush logic
involving offsets and overlaps.

Acked-by: Deepika Singh <dsi@qti.qualcomm.com>
Change-Id: I1e5ac1e3c52c80d40b6c3a0c9207e7a73d06bf65
Signed-off-by: Mohammed Nayeem Ur Rahman <mohara@codeaurora.org>
2020-03-27 15:59:12 +05:30
Mao Jinlong
0a667f9293 defconfig: Enable mem_dump driver on gki build for lahaina
Enable memory dump driver to be build as a module in the defconfig
on Lahaina.

Change-Id: I284e5d082d5a595f794b15fd66163137596e714e
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
2020-03-27 14:57:25 +08:00
Mao Jinlong
a4f0a38f21 soc: memory_dump: Add moudle support for mem_dump driver
Add support to build the memory dump driver as moudle on gki build.

Change-Id: I8cf227d0b0044b935bbf224d1191ec84fa497509
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
2020-03-27 14:56:22 +08:00
qctecmdr
98e5858717 Merge "arm64: defconfig: Enable QVR HID driver on Lahaina" 2020-03-26 20:45:05 -07:00
qctecmdr
e86a371037 Merge "msm: pcie: correct PCIe1 and PCIe2 clock order" 2020-03-26 20:45:05 -07:00
qctecmdr
528b8e5226 Merge "mmc: sdhci-msm: Avoid enable SD card power if card is removed" 2020-03-26 20:45:05 -07:00
qctecmdr
c1f9871880 Merge "mhi: core: Skip handling MSI0 if MHI register access is not allowed" 2020-03-26 20:45:04 -07:00
rbandi
39a940990e HID: qvr: Removing axis orientation
Driver reports sensor data without modifying the
orientation of axes.

Change-Id: I3e0d3d3efc848d7e72a1edda9f168721dbccb308
Signed-off-by: rbandi <rohitbandi@codeaurora.org>
2020-03-26 19:24:13 -07:00
Prakruthi Deepak Heragu
e26e8510ee arm64: defconfig: Add support for LKDTM on Lahaina
Enable LKDTM module for various test cases in the qgki-debug
configuration of Lahaina.

Change-Id: Id0479ec95d8410e52bc270f907e8a537e73d0fb3
Signed-off-by: Prakruthi Deepak Heragu <pheragu@codeaurora.org>
2020-03-26 13:29:28 -07:00
Srinivas Rao L
12e3fa438e pinctrl: qcom: Add GPIO wakeup interrupt map for Shima
GPIOs that can be configured as wakeup sources, have their
interrupt lines routed to PDC interrupt controller. Add the
interrupt map of the GPIO's to its wakeup capable interrupt
parent.

Change-Id: I6680a6d55f53936ace4daab1f2365de055a89a06
Signed-off-by: Srinivas Rao L <lsrao@codeaurora.org>
2020-03-26 15:01:57 +05:30
Srinivas Rao L
4acf052c6e drivers: irqchip: qcom-pdc: Add PDC IRQ chip support for shima
Add PDC interrupt controller chip support for shima.

Change-Id: I8d92ccba39ac09eede3236780f0509f6a4b117f1
Signed-off-by: Srinivas Rao L <lsrao@codeaurora.org>
2020-03-26 14:58:14 +05:30
Tao,Zhang
8702e88c20 coresight: cti: Correct checking return value of device resume
The return value of device resume function should be greater than
or equal to 0. Correct the conditional judgment to allow the return
value to be greater than 0. Otherwise, it can cause cti fail to
pass test sometimes.

Change-Id: I195b192d438b954c02c9d2cda2906075e8688ac9
Signed-off-by: Tao,Zhang <taozha@codeaurora.org>
2020-03-26 00:25:26 -07:00
Bhaumik Bhatt
01e0ee4292 mhi: core: move non-essential errors to log messages
With the exception of control event ring processing, turn
the non-essential error messages to log variants so they
do not show up in dmesg.

Change-Id: Ib49022b25817d8d65dd10d33c4a948698c571082
Signed-off-by: Bhaumik Bhatt <bbhatt@codeaurora.org>
2020-03-25 19:41:58 -07:00