Configure the IPCC summary IRQ as wakeup capable interrupt.
IPCC interrupt needs to wake up the device from low power
modes when wakeup capable event is generated from remote
subsystem.
Change-Id: Iaffefc6ef68743c7de11062c39e2b1453c58b9a1
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
[eberman@codeaurora.org: Resolve merge conflicts]
Signed-off-by: Elliot Berman <eberman@codeaurora.org>
Add check of trace unit power property to enable/disable that
keep the trace unit powered.
Change-Id: I66dbfee16df63480c9309092e61ee39b8b0cd6e8
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
Since the tcs_in_use flag is authoritative enough to determine the
idleness of the TCS, avoid reading the register redundantly.
Change-Id: Ic7737e60ca0029b3cf9d1cc9e613435608be7bc8
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
For RSCs that have sleep & wake TCS but no dedicated active TCS, wake
TCS can be re-purposed to send active requests. Once the active requests
are sent and response is received, the active mode configuration needs
to be cleared so that controller can use wake TCS for sending wake
requests in 'solver' state while executing low power modes.
Change-Id: I0d15c290db48d08158fdbff2cd91505563dc3fd5
Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org>
Controllers may be in 'solver' state, where they could be in autonomous
mode executing low power modes for their hardware and as such are not
available for sending active votes. Device driver may notify RPMH API
that the controller is in solver mode and when in such mode, disallow
requests from platform drivers for state change using the RSC.
Change-Id: I6dccfabdf230d927b945b0bd1840233e69064c9d
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org>
When triggering a TCS to send its contents, reading back the trigger
value may return an incorrect value. That is because, writing the
trigger may raise an interrupt which could be handled immediately and
the trigger value could be reset in the interrupt handler.
A write_tcs_reg_sync() would read back the value that is written and try
to match it to the value written to ensure that the value is written,
but if that value is different, we are stuck in loop forever.
Change-Id: I54866b9b9d85fa79c8df84aecd502764b9f9158a
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Add support to new register memory map, fix loop offset and
dynamic number of link list.
Change-Id: Ibadfa723842dae80cdd50bf08018d86c2ef30b94
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
Add dt binding head file for dcc driver. It's used by device tree
to define dcc link list.
Change-Id: Iacbfeeb2cf2763608f075f2828a8d47d662fa88f
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
Add qseecom.h, qcedev.h, fips_status.h for Lahaina bring up
Change-Id: I21c1747e7ce9fab1d190b8ea54ac2d54c11bd44f
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
For GDSCs that reside on domains that are collapsible and
support a minimum voltage of retention, explicitly vote on
the minimal operating voltage, LowSVS for the rail. This is
required as an interim step before enabling/disabling the
GDSC. Once that's done and the GDSC has latched on to its
new state, remove this voltage vote.
Note that this fix-up patch has been squashed in:
commit c7d3dc884292 ("clk: qcom: gdsc: Fix issue with
dereferencing NULL pointer in gdsc APIs").
Change-Id: Ibac43bba8248d68f8355d1a9db9cfcbfb9fa7557
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
[collinsd@codeaurora.org: squashed in a fix-up patch]
Signed-off-by: David Collins <collinsd@codeaurora.org>
Support globally distributed switch controller(GDSC) devices as
regulators. This will enable clients to use the regulator framework
APIs to enable/disable the GDSCs.
The hw_ctrl/domain_ctrl registers which might be required to be
enabled before the GDSC are modelled using syscon framework.
Change-Id: I2d63105d032ab16d5555722680f4371c831823cd
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
[collinsd@codeaurora.org: removed clk_set_flags() calls]
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add new ops to allow clock clients to enable/disable hardware
dynamic gating of the clock branch.
Change-Id: I14abed3827de8cefc31f3deb3c1e589136c32b8d
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
Currently, if clk_set_rate() is called on a disabled clock that
has flags = FORCE_ENABLE_RCG, the rate is neither physically set
nor properly cached in software. This means that when the clock
is later enabled, its rate will not be what was previously
requested.
Change the handling of FORCE_ENABLE_RCG so that all clk_set_rate()
calls are respected regardless of a clock's enable state. In
doing so, ensure that FORCE_ENABLE_RCG and enable_safe_config are
supported both individually and together.
Implement the following behavior:
enable_safe_config == true:
enable - configure the RCG according to the cached current_freq
disable - configure the RCG for CXO (safe) source
set_rate - (if prepared) configure the RCG for the requested rate
(if not prepared) cache the rate in current_freq
flags | FORCE_ENABLE_RCG:
enable - set ROOT_EN=1 to force the RCG to be enabled
disable - set ROOT_EN=0
set_rate - configure the RCG for the requested rate;
if disabled, then set ROOT_EN=1 before the
configuration is changed and ROOT_EN=0 after
enable_safe_config && (flags | FORCE_ENABLE_RCG):
enable - set ROOT_EN=1 and configure the RCG according to the
cached current_freq
disable - configure the RCG for CXO source and set ROOT_EN=0
set_rate - (if prepared) configure the RCG for the requested rate
(if not prepared) cache the rate in current_freq
Change-Id: Ib7442e4a4b572ae7c567929044410e09a9886c76
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add a flag to indicate to support and enable hardware control mode
of an RCG.
Change-Id: I21194a463441ea13b7575a4174b1f96504b42b1e
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The commit 7533b7fb5495 ("clk: qcom: clk-rcg2: Read RCG source before
calculating clk rate")' had introduced a function to update the src map,
but there could be a race where a set_rate for a clock from a particular
CC on a CPU could override the global cxo_f which was set by clock
enable/disable for a clock from another CC.
Change-Id: Id86818895e226a387e7fd1a09e2034eee18fd361
Signed-off-by: Taniya Das <tdas@codeaurora.org>
If the clock rate is set previously to hlos and enable
safe config is true. In that case we need to check the
rcg source to make sure recalc will return correct rate.
Rate calculation is done based on selected source rather
than 19.2 MHZ. Also, we are setting correct src value for
XO based on the parent map of a particular clock.
Change-Id: Id6d2923136a0848d55cff37fb5ef2e3b092af27a
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
There could be cases where a simultaneous clk_disable and clk_set_rate on
the same rcg could result in a wrong recalc rate. So for shared rcgs
get the pre_div value based on the current frequency from the frequency
table.
Change-Id: Ia5730e43965b2d0ba19da05fca47825514f98865
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The Alpha BW for Fabia PLL is 16 bit and the calculated hw rate has
additional KHz of frequency. Due to this additional frequency, the
source is wrongly selected. Truncate the additional KHz using the
DIV_ROUND_CLOSEST_ULL.
Change-Id: Ic9c523c87277c4813b676cf8a52a1207e8f1ecc2
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
Add null pointer checks for the parent clock pointers returned
by clk_hw_get_parent() and clk_hw_get_parent_by_index() in
several qcom clock drivers.
Change-Id: I869c9e35b7ec083b34bcc70d18601aec64c3ac97
Signed-off-by: David Collins <collinsd@codeaurora.org>
Move reading of MN counter mode register earlier to source sel
to fix overwrite of MN counter mode variable.
Change-Id: I5a318112e85c4af83fdbf9bba8770f4ec1b84326
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
