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Author SHA1 Message Date
qctecmdr
28c5ea1f0c Merge "dt-bindings: usb: Add Gen2 Tx Compliance tuning property for dwc3" 2020-04-05 07:27:26 -07:00
qctecmdr
4ab56b369d Merge "ARM: dts: msm: Increase the dwc3 reg address range for Lahaina" 2020-04-05 07:27:26 -07:00
qctecmdr
ddef505daf Merge "dt-bindings: LLCC: Add "qcom,shima-llcc" compatible property" 2020-04-04 10:08:51 -07:00
qctecmdr
bb4648d73b Merge "ARM: dts: msm: Disable tpdm ddr for lahaina" 2020-04-04 10:08:51 -07:00
qctecmdr
d813d1b8ab Merge "ARM: dts: msm: add capacity and DPC properties for Shima" 2020-04-04 10:08:51 -07:00
qctecmdr
8e89886020 Merge "ARM: dts: msm: Add device trees for LahainaP variant" 2020-04-04 01:02:02 -07:00
qctecmdr
8945e18fae Merge "ARM: dts: msm: Add pshold to Shima" 2020-04-03 15:20:01 -07:00
Elliot Berman
295665f6fd ARM: dts: msm: Add device trees for LahainaP variant 
Add device tree support for LahainaP variant (no modem).

Change-Id: I9bafe2b27653041831bc424cbda1167f3948e65b
 2020-04-03 11:13:28 -07:00
Elliot Berman
98303fba40 dt-bindings: msm: Add compatible strings for lahainap 
Add compatible stings for lahainap.

Change-Id: I3412619f8423ef3ed4c0055f1041cc9e0c531efe
 2020-04-03 11:13:13 -07:00
qctecmdr
86d7911d43 Merge "ARM: dts: msm: enable qmap flow control feature" 2020-04-03 09:15:56 -07:00
qctecmdr
c56d092a10 Merge "dt-bindings: clock: Add rpmh clock bindings for Shima" 2020-04-03 09:15:56 -07:00
qctecmdr
ce226b8768 Merge "ARM: dts: msm: Update the GSI gpii mask for lahaina" 2020-04-03 09:15:56 -07:00
Pavankumar Kondeti
d56318ef3f ARM: dts: msm: add capacity and DPC properties for Shima 
The "capacity-dmips-mhz" and "dynamic-power-coefficient" are
used to build Energy Model which in turn used by EAS to take
placement decisions.

Change-Id: Ia44ffe4fcb799663c4bb47eb18f1ac79952ed12d
 2020-04-03 15:47:31 +05:30
Chandra Sai Chidipudi
f3bd9d19e0 dt-bindings: LLCC: Add "qcom,shima-llcc" compatible property 
Add "qcom,shima-llcc" compatible property which matches
the driver for Shima platform.

Change-Id: Ie0711695459cd59574b4ca9e4cf3f049b5618544
 2020-04-03 09:50:03 +05:30
Mao Jinlong
f62264a76b ARM: dts: msm: Disable tpdm ddr for lahaina 
Disable tpdm ddr to avoid register access issue.

Change-Id: Ie7a0922f3d7b09d2c75005d5393576dd424a0e2a
 2020-04-02 05:51:44 -07:00
qctecmdr
12f20880a6 Merge "ARM: dts: msm: Add core hang detection to dt for Shima" 2020-04-02 05:43:11 -07:00
qctecmdr
3b1ab8a602 Merge "ARM: dts: msm: Move qbt_handler to soc" 2020-04-02 05:43:11 -07:00
qctecmdr
78d6cd5f39 Merge "Revert "ARM: dts: msm: Clean-up vidc DT node"" 2020-04-02 05:43:11 -07:00
qctecmdr
7b01ccb46e Merge "ARM: dts: msm: Add support for ION for the trusted-VM" 2020-04-02 05:43:11 -07:00
Elson Roy Serrao
d1992a3331 dt-bindings: usb: Add Gen2 Tx Compliance tuning property for dwc3 
Tuning for Tx 3.1 Gen2 needs to be done by modifiying the deemph
registers. Expose these registers via device tree properties so that
tuning can be applied duing dwc3 init.

Change-Id: I84066e976ccbd6006ca9149e29d1c27acb694646
 2020-04-01 15:56:21 -07:00
qctecmdr
f0227e9ddd Merge "ARM: dts: msm: use 'dma-coherent-hint-cached' for fastrpc nodes" 2020-04-01 13:43:11 -07:00
Elson Roy Serrao
9844984a79 ARM: dts: msm: Increase the dwc3 reg address range for Lahaina 
The register address range for Lahaina is not covering all the
controller registers. Tuning the Tx deemph registers for dwc3
gen2 protocol test is not possible with the current range.
Modify the reg property to cover the entire range as defined in
the data book to fix this issue.

Change-Id: I34b605f920af7cae8b2efd69a54f96e8cde5c001
 2020-04-01 11:50:45 -07:00
Mihir Ganu
b55a6ef70a Revert "ARM: dts: msm: Clean-up vidc DT node" 
This reverts commit 789a5cb2fd.

Change-Id: I59c3a194bcafbe4d5e36c6a847ecc8a661722915
 2020-04-01 09:30:46 -07:00
qctecmdr
28ac5c4ad8 Merge "Revert "dt-bindings: msm: vidc: Clean-up dt properties"" 2020-04-01 02:51:02 -07:00
Mukesh Ojha
d0179ec286 ARM: dts: msm: Add pshold to Shima 
Add pshold node to Shima devicetree.

Change-Id: Ifaf3c87e4a4fd334952801298700113e8bd5ed71
 2020-04-01 14:35:39 +05:30
Mukesh Ojha
c3f70428c7 ARM: dts: msm: add msm_rtb tracing 
Add qcom,msm-rtb entry to device tree to enable msm_rtb tracing.

Change-Id: Iad117ffb05d477f0ad960737782c56944f3db93e
 2020-04-01 14:34:52 +05:30
Mukesh Ojha
f982a9bb94 ARM: dts: msm: Add core hang detection to dt for Shima 
Add qcom,msm-hang-detect to device tree to enable MSM Core Hang
Detection on all cores.

Changed from 2 nodes (one for each of silver and gold) to
1 node because that's semantically correct for the driver.

Change-Id: I063d7cc244a0b5d12971f393f45053914fa53179
 2020-04-01 14:32:50 +05:30
Abir Ghosh
53a6ca4dc3 ARM: dts: msm: Move qbt_handler to soc 
Define the dtsi for qbt_handler inside
soc.

Change-Id: I9ff1ab103c55a4424fe7c1571d15622c9106ea2d
 2020-04-01 12:22:12 +05:30
qctecmdr
91fc104583 Merge "ARM: dts: msm: define continuous splash memory region for lahaina" 2020-03-31 21:53:23 -07:00
Himateja Reddy
c2fb8297f7 ARM: dts: msm: use 'dma-coherent-hint-cached' for fastrpc nodes 
Use 'dma-coherent-hint-cached' instead of 'dma-coherent' for the
fastrpc iommu context banks.

Now, on a QGKI kernel, cached ION buffers will be DMA mapped as
IOMMU cached for the fastrpc devices, all other buffers will be
DMA mapped as IOMMU uncached and dma_alloc_attrs will always
return memory with a cached CPU mapping as well as DMA mapping
its memory as IOMMU cached.

On a GKI kernel, all buffers for fastrpc devices will be DMA
mapped as IOMMU uncached and dma_alloc_attrs will always return
CPU uncached memory.

Change-Id: I4c5b3e082dc057cb76bfd039b19c6211c729597f
Acked-by: Thyagarajan Venkatanarayanan <venkatan@qti.qualcomm.com>
 2020-03-31 12:01:20 -07:00
Mihir Ganu
6c1f6a25b8 Revert "dt-bindings: msm: vidc: Clean-up dt properties" 
This reverts commit 75bc943da9.

Change-Id: Ifcbcb32d70d4c5515b0c1de8f31aa79081507656
 2020-03-31 11:52:57 -07:00
qctecmdr
2b69bf338f Merge "ARM: dts: msm: remove CX, MX and MMCX always-on configuration for Lahaina" 2020-03-31 11:49:53 -07:00
Taniya Das
125b8bea24 dt-bindings: clock: Add rpmh clock bindings for Shima 
Add binding documentation for clock rpmh driver on Shima.

Change-Id: I24d46ba1040915bdc8056e1431a751512143de92
 2020-03-30 21:58:35 +05:30
qctecmdr
598af0515a Merge "dt-bindings: pmic-glink: add subsystem restart (SSR) support" 2020-03-30 07:21:10 -07:00
qctecmdr
d5b6364702 Merge "ARM: dts: msm: Add regulators for sa8155" 2020-03-30 07:21:09 -07:00
qctecmdr
0044a473f1 Merge "ARM: dts: msm: Remove spss glink ssr entry for Lahaina" 2020-03-29 21:21:56 -07:00
qctecmdr
58642255ff Merge "ARM: dts: msm: Add RSC device bindings for Shima" 2020-03-29 21:21:56 -07:00
Zhiqiang Tu
0275307f51 ARM: dts: msm: Add regulators for sa8155 
Add rpmh and refgen regulators for sa8155

Change-Id: Iea8fa84200127394dca1029abf02457bcd3d31ff
 2020-03-29 22:17:24 +08:00
qctecmdr
121f0021d1 Merge "ARM: dts: msm: Add snapshot of all SM8150 and SA8155 DT files" 2020-03-29 00:33:16 -07:00
qctecmdr
1c3c85283f Merge "ARM: dts: msm: add swr dmic's as codecs" 2020-03-29 00:33:16 -07:00
qctecmdr
82d9e78962 Merge "dt-bindings: qpnp-lcdb-regulator: Add LCDB regulator documentation" 2020-03-28 07:28:11 -07:00
qctecmdr
3b9beea6d0 Merge "ARM: dts: msm: Add initial ION heaps for Shima" 2020-03-28 07:28:11 -07:00
Jay Jayanna
55d2ef5f25 ARM: dts: msm: Remove spss glink ssr entry for Lahaina 
Remove spss glink ssr entry as the dependencies are not
present on the present branch.

Change-Id: Ia47aa1d5683eac16a5c0d0e865761d1fad496149
 2020-03-27 18:11:09 -07:00
qctecmdr
92076541c5 Merge "ARM: dts: qcom: modify initramfs size" 2020-03-27 03:47:17 -07:00
Vivek Kumar
3375ee9e11 ARM: dts: msm: Add snapshot of all SM8150 and SA8155 DT files 
Add snapshot of all SM8150 and SA8155 base device tree files
from msm-4.14, also add relevant changes in the makefile.

Change-Id: I91fb065ebbb70f789afcb126e27fb928fe8d4929
 2020-03-26 22:23:05 -07:00
qctecmdr
2294b1ed91 Merge "bindings: sound: Add swr-haptics binding document" 2020-03-26 20:45:04 -07:00
qctecmdr
07554f1a62 Merge "ARM: dts: qcom: add sde-rsc-rpmh driver to disp_rsc node" 2020-03-26 20:45:04 -07:00
Bojun Pan
05a7a16c8e ARM: dts: msm: enable qmap flow control feature 
Enable the rmnet_ctl pipes setups and functionalities.

Change-Id: I2b4b1a93f7c2bc3c6aebf71b31aac1a05afe1f2e
 2020-03-26 14:00:32 -07:00
Srinivas Rao L
c07590dcaa ARM: dts: msm: Add RSC device bindings for Shima 
Add Apps and Display RSC device bindings for Shima.

Change-Id: I18957f0ef47ee82f747d1c03c0e4c8019f187cb9
 2020-03-26 11:09:37 +05:30
Srinivas Rao L
d96175ec67 ARM: dts: msm: Add wakeup parent for Shima TLMM 
Add wakeup parent irqchip for Shima TLMM as PDC.

Change-Id: I38bb470119faed3af8168a4cd9f9a3e74571107a
 2020-03-26 11:09:31 +05:30