This reverts commit b9b4ade986.
Older ver of SNPS core needs viewport registers as it does not
have separate iATU region. Hence keep the viewport support.
Change-Id: Ic863eb3332c54df433726064591a01dc50d29565
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
enable qcom_scm and fastcvpd for vidc driver.
Change-Id: Idb17a079e1472e1d2a853d2ea68da6933768d7e1
Signed-off-by: Laisheng Hu <laisheng@codeaurora.org>
Consider a case where ep0 is not in setup stage and composition
switch happens. Currently DWC3_DEPCMD_ENDTRANSFER command is not
issued on ep0 which means that the transfers are not flushed out
and driver clears the run/stop bit hence stopping the controller.
Now as soon as driver sets the run/stop bit controller tries to
access the trb from the previous session which is already unmapped
resulting in SMMU fault.
Fix this by unconditionally issuing DWC3_DEPCMD_ENDTRANSFER
command on ep0. Although it is not specified in the data book
but if we know for sure that we are anyway going to stop the
controller then we can issue ENDTRANSFER command on ep0.
Change-Id: Ic6ee570acc8926897d3b6042181a501a47438d92
Signed-off-by: Pratham Pratap <prathampratap@codeaurora.org>
This can ease the complexity to port CNSS2 driver to non-MSM
platforms while still be able to maintain the compatibility.
Change-Id: I268cdd90c59085b34aa2fe3c3b845d60c4e2a417
Signed-off-by: Yue Ma <yuem@codeaurora.org>
Since there may be link issues if QCA6490 device boots up with Gen3
link speed, always set initial target PCIe link speed to Gen2. Device
is able to change it (back) later at any time if needed.
Change-Id: I9d617d71926fe98e59e67aff772984878e0a2689
Signed-off-by: Yue Ma <yuem@codeaurora.org>
Remove CONFIG_SLUB_DEBUG_ON from debug variant for performance
reasons. Also remove redundant HARDENED_USERCOPY from debug config
since this gets copied over from the standard config.
Change-Id: I7c6fc8620290cf126ced046f82811e9e39bc2a60
Signed-off-by: Dennis Cagle <dcagle@codeaurora.org>
There are usecases where clients want to change the maximum GEN
speed that PCIe can link up with. Provide clients the ability to
control the maximum PCIe GEN speed to for such usecases.
Change-Id: I834bee2063133546c9b0ebac2d5328ffbc5ceac6
Signed-off-by: Tony Truong <truong@codeaurora.org>
In HS Only mode of dwc3 controller version 1.9A, UTMI clock needs
to be selected before core soft reset as per the HPG sequence.
Or else the core soft reset fails, leading to enumeration
failure. Hence select UTMI clock before performing
SOFT_RESET operation.
Change-Id: I12d4a992872eecbfc38825282559cd4d592c3896
Signed-off-by: Elson Roy Serrao <eserrao@codeaurora.org>
For non-MSM platforms, PCI wake GPIO may not be handled by PCI root
complex driver so add support to handle it in device driver.
Change-Id: Ief6bc6b25bdc5b93887af1cc626acc721f9fa85a
Signed-off-by: Yue Ma <yuem@codeaurora.org>
This makes sure CNSS2 driver is able to work in the platforms and
kernels which do not have on-chip interconnect management feature.
Change-Id: I282ef1a282fab9ce4910e7ab914f26789b34ba64
Signed-off-by: Yue Ma <yuem@codeaurora.org>
This makes sure CNSS2 driver is able to work in non-MSM platforms
which do not have command DB feature.
Change-Id: I9551bfc639e6db0256e475a27db5dec87bce74ed
Signed-off-by: Yue Ma <yuem@codeaurora.org>
This makes sure CNSS2 driver is able to work in non-MSM platforms
which do not have IPC logging feature.
Change-Id: I4c8fe3eb45e38fd106f47c28f0e4da82b0bdf76f
Signed-off-by: Yue Ma <yuem@codeaurora.org>
This makes sure CNSS2 driver is able to work in non-MSM platforms
which do not have memory dump and mini dump features.
Change-Id: I5193deed941ff8e2e2ca2693150396a53eb3db7d
Signed-off-by: Yue Ma <yuem@codeaurora.org>
Currently in MSM platform reserved memory is attached to PCI
device of_node which may not apply to other non-MSM platforms.
Hence abstract the API using CONFIG_ARCH_QCOM flag.
Change-Id: Ic02b087c188b8dcb0959e17c80e72bb4021a725c
Signed-off-by: Yue Ma <yuem@codeaurora.org>
