Commit graph

1,834 commits

Author SHA1 Message Date
qctecmdr
89a9afa727 Merge "disp: msm: sde: disable uidle for yupik target" 2021-01-20 22:56:44 -08:00
Andhavarapu Karthik
c771326b63 disp: msm: sde: disable uidle for yupik target
Made changes to disable uidle feature in yupik target.

Change-Id: If122a86ed14002399e2dbd0b62385d47c854136f
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
2021-01-20 15:56:47 +05:30
Yashwanth
7277a3f2f2 disp: msm: sde: save register write logs in dump
Changes are made to add register write logs to memory dump.
This can be extracted from crash dumps and used for analysis.

Change-Id: If46aaa4ae68f83c79d4b51cbe5dfd22340aa991d
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-01-18 16:50:39 +05:30
Narendra Muppalla
286a52ba84 disp: msm: sde: use different spin lock for frame events
Due to lock sequence inconsistency between sde_crtc->spin_lock and
sde_kms->hw_intr->irq_lock can cause deadlock, to avoid this possible
deadlock this change uses different spin lock for frame events.

Change-Id: I51b1184dfa1069c87653099b95b992b277721daf
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2021-01-16 20:20:58 -08:00
qctecmdr
87440766f3 Merge "disp: msm: dp: add support for 7nm pll" 2021-01-14 23:05:05 -08:00
qctecmdr
a5441c0cba Merge "disp: msm: sde: fix potential race condition" 2021-01-14 23:05:05 -08:00
Rajat Gupta
557d8d3fa5 disp: msm: dp: add support for 7nm pll
Add support for 7nm pll. Only some offsets are different from 5nm
pll while the rest are same.

Change-Id: If61cd604d7f8221c659f1b83761647e86e3b6627
Signed-off-by: Rajat Gupta <rajatgu@codeaurora.org>
2021-01-14 02:54:05 +05:30
Andhavarapu Karthik
aa20b1c188 disp: msm: sde: add cwb virtual mixers support
In yupik target, cwb path has pingpong block without any layer mixer.
Add virtual mixer to support reservation of pp block in such case.
This virtual mixer will be used only for cwb use case.

Change-Id: Iacc1a3f5e7d99d9fc36288450b0e19081b3ef763
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
2021-01-13 14:00:22 +05:30
Ping Li
6a80184cdb disp: msm: sde: fix potential race condition
Move the hist irq handling out of callback function, i.e., the hw
interrupt irq_lock context, to avoid dead lock between crtc spin_lock
and irq_lock. This change also extends crtc spin_lock coverage in
_sde_cp_crtc_enable_hist_irq to prevent null pointer dereference on
event node, which can be deleted during crtc event de-registration.

Change-Id: Iadaed54ab93c4c4abe065a8762d2addccb0c65c6
Signed-off-by: Ping Li <pingli@codeaurora.org>
2021-01-12 18:40:18 -08:00
qctecmdr
5dcc9ed436 Merge "disp: msm: clear dma done interrupt status for slave controller" 2021-01-11 05:47:59 -08:00
Harigovindan P
1b9d765763 disp: msm: clear dma done interrupt status for slave controller
When Broadcast is enabled, DMA_DONE bit gets set for slave
controller on command transfer completion but it is not
getting cleared. Due to this, DMA transfer failures on slave
controller are not getting caught. This patch add supports for
clearing DMA_DONE for slave controller on every successful
transfer. This also prints error if transfer fails on slave
controller.

Change-Id: I61ce7b2d8be323adc70d888b5a2416afd9ae9fac
Signed-off-by: Harigovindan P <harigovi@codeaurora.org>
2021-01-07 13:40:25 +05:30
Dheeraj Madiraju
93f543c055 disp: msm: sde: add hdr flags for yupik
Add hdr flags for yupik.

Change-Id: Ica8d752499dae5d80d99f3f0caccbbfed4e539ec
Signed-off-by: Dheeraj Madiraju <dmadiraj@codeaurora.org>
2021-01-07 09:42:43 +05:30
qctecmdr
0053412244 Merge "disp: msm: sde: replace demura pipe index cap. with general pipe index" 2021-01-05 20:41:24 -08:00
qctecmdr
54b6925e51 Merge "techpack: Install headers for display techpack" 2021-01-05 00:59:32 -08:00
qctecmdr
65c84a87ee Merge "disp: msm: sde: perform cmd encoder disable only for master" 2021-01-05 00:59:32 -08:00
Andhavarapu Karthik
d92bb74dfd disp: msm: sde: add rev check for mdp in yupik target
Add required revision checks for mdp in yupik target.

Change-Id: I2747a0addfb3b4880397d56b18a9e9aa9644df34
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
2020-12-31 16:45:40 +05:30
Raviteja Tamatam
49e09fde9d disp: msm: sde: perform cmd encoder disable only for master
In dual DSI cases sde_encoder_helper_phys_disable needs to be
called only for master encoder.

Change-Id: If2d327a4800914fe365c6877bf7854275a4434ae
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
2020-12-28 18:50:25 +05:30
qctecmdr
8acd9ca084 Merge "display: msm: sde: update qos lut after scaler config" 2020-12-21 19:51:34 -08:00
qctecmdr
71d4e079bf Merge "disp: msm: dp: log the dp mst connector id information" 2020-12-21 10:09:14 -08:00
Abhijit Kulkarni
80bf89b836 display: msm: sde: update qos lut after scaler config
This change moves the code of updating the qos lut for qseed3
to each plane after updating the scaler configuration. This
avoids using stale values for qos settings.

Change-Id: I2c55a98e1ba9790d596c55160933cd5afd2388e5
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-12-21 09:38:38 -08:00
qctecmdr
91d1ed8e79 Merge "disp: msm: dsi: avoid debugfs HW access based on HW ownership" 2020-12-21 04:42:30 -08:00
Sankeerth Billakanti
c6d5c4d121 disp: msm: dp: log the dp mst connector id information
Logging connector id will help debug the issues related to
DP MST stability and pre-merge tests. This change will log
the DP MST connector IDs modified during stability tests.

Change-Id: Ifaf8e319697a809b02c24c473acec8da521286e2
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
2020-12-20 14:30:14 +05:30
qctecmdr
eb21ca8701 Merge "disp: msm: sde: add scaler3_cfg and pixel_ext to sde plane" 2020-12-18 12:26:56 -08:00
Veera Sundaram Sankaran
35d1cdafd9 disp: msm: dsi: add stub function parse power_cfg in trusted-vm
In trusted-vm, there are no power cfg entries in device-tree as
there is no support. Add stub function to avoid parsing errors
related to power cfg in trusted-vm.

Change-Id: Id28ad9a4d5608d561e22b318a08c6bc1ccc5f2ee
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-12-17 15:28:04 -08:00
Veera Sundaram Sankaran
8f95751727 disp: msm: dsi: avoid debugfs HW access based on HW ownership
Add VM ownership checks before accessing the HW through the debugfs
path in dsi display/ctrl modules to avoid illegal access.

Change-Id: Ia6e2ab0ef60d0f11e5945a63885d939db2ef78b0
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-12-17 15:23:03 -08:00
Veera Sundaram Sankaran
4c29eaf3b0 disp: msm: avoid sde_dbg HW access based on HW ownership
Add VM ownership checks before accessing the HW through the debugfs
path in sde dbg module to avoid illegal access. Set the ownership
status on bootup based on the VM.

Change-Id: I30f2a1eb7e049740f1f7fe3ed03aa411264ba7b3
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-12-17 15:23:03 -08:00
Veera Sundaram Sankaran
3c1c4cd333 disp: msm: sde: avoid sde debugfs register access based on HW ownership
Add VM ownership checks before accessing the HW through the debugfs
path in sde crtc/encoder/connector modules to avoid illegal access.

Change-Id: I4ff8f29353835d263beb2091bdeec40125addbf8
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-12-17 15:23:03 -08:00
Manoj Kumar AVM
8ff6634a86 techpack: Install headers for display techpack
These can be reference with the qti_display_kernel_headers header
library.

Change-Id: Id8b983bb2c7d9d3f999d93b88de953a8b606aa1b
Signed-off-by: Manoj Kumar AVM <mkavm@codeaurora.org>
2020-12-17 13:50:14 -08:00
Rajeev Nandan
4060bdee77 Revert "disp: msm: dsi: move backlight operations to post kickoff"
This reverts commit e60959b052.

Change-Id: I539522a6a01297fecfafb446a44e725679bc39c0
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
2020-12-15 18:06:04 +05:30
Christopher Braga
26c92ca5c2 disp: msm: sde: replace demura pipe index cap. with general pipe index
Generalize the demura pipe index capability on sde_plane objects to
instead provide the relative pipe index for all plane types. This
information can be used by clients to fully determine a plane type
and its position.

Change-Id: I597da0dab92c249b16934b9327353e4937635606
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2020-12-14 18:42:10 -05:00
Xiaowen Wu
1661be9086 disp: msm: sde: add scaler3_cfg and pixel_ext to sde plane
Add scaler3_cfg and pixel_ext to sde plane to avoid updating state
variables in commit thread. This fixes atomic check failure when
scaler lut is not set.

Change-Id: I936b124ca6f90af22a87df31536204e837422a70
Signed-off-by: Xiaowen Wu <wxiaowen@codeaurora.org>
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-12-14 12:41:13 -08:00
qctecmdr
554a3b8b06 Merge "disp: msm: dp: validate edid before dereferencing" 2020-12-14 09:56:07 -08:00
qctecmdr
e0695d4236 Merge "disp: msm: sde: cleanup ctl/intf registers on cmd encoder disable" 2020-12-12 22:39:19 -08:00
qctecmdr
93331df7d7 Merge "disp: msm: dsi: enable DMA cmd scheduling for video mode panels" 2020-12-11 09:49:33 -08:00
Rajeev Nandan
e60959b052 disp: msm: dsi: move backlight operations to post kickoff
This change moves the backlight update operation from
drm bridge enable to connector post kickoff.

When timing engine is enabled with programmable fetch
enabled, the timing engine will start counting from
the prog_fetch_start point (which is somewhere in VFP).
It’s a grey area from that point to the actual panel
vsync and SW should not trigger DMA command during that
time.

During display resume, sometimes the INTF timing engine
do not get enabled completely at the first vblank irq.
The backlight update cmd transfer trigger as part of the
drm bridge enable can also take place at the same time,
that may cause DSI cmd transfer failure.

Change-Id: I2722d3c23012ef0e7bcc7f728ec5658318ce4e60
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
2020-12-11 12:14:54 +05:30
Veera Sundaram Sankaran
030e3f15a7 disp: msm: sde: cleanup ctl/intf registers on cmd encoder disable
The SDE RM determines the number of displays enabled in cont-splash by
checking the INTF_ACTIVE bits in the ctl. The trusted-vm relies on the
same cont-splash path during transitions and the stale ctl INTF_ACTIVE
on dual display usecases leads to wrong status check. Currently, only
video/wb encoders use the phys_encoder disable helper during encoder
disable to clear out few ctl/intf registers. Extend it for cmd encoder
as well to remove the stale entries.

Change-Id: I7f21ef46178ce3943ee85abdf29f7cdef93d7c52
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-12-10 18:37:34 -08:00
Rajeev Nandan
37b2f80ad4 disp: msm: dsi: enable DMA cmd scheduling for video mode panels
This change enables the DMA CMD scheduling as default for
video mode panels.

In video mode panel, if the DMA is triggered very close to
the beginning of the active window and the DMA transfer
happens in the last line of VBP, then the HW state will
stay in ‘wait’ and return to ‘idle’ in the first line of VFP.
But somewhere in the middle of the active window, if SW
disables DSI command mode engine while the HW is still
waiting and re-enable after timing engine is OFF. So the
HW never ‘sees’ another vblank line and hence it gets
stuck in the ‘wait’ state.
Scheduling the DMA cmd to the first line in VFP fixes
this issue.

Change-Id: If9e5bd1923c012f10dee50c791a2b2b001d97553
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
2020-12-10 04:19:33 -08:00
qctecmdr
5caf284ecc Merge "disp: msm: dp: handle link maintenance failures" 2020-12-08 04:44:42 -08:00
qctecmdr
a493aaf3a2 Merge "disp: msm: sde: flush all event thread work during CRTC disable" 2020-12-08 04:44:42 -08:00
qctecmdr
874ebfeeae Merge "disp: msm: dp: fix page fault from hdcp buffer access" 2020-12-08 04:44:42 -08:00
qctecmdr
285589db6a Merge "disp: msm: sde: update encoder atomic check during qsync usecase" 2020-12-07 23:37:28 -08:00
qctecmdr
59a266aa8e Merge "disp: msm: dsi: Add support for 5nm C-PHY shadow clock" 2020-12-07 17:09:16 -08:00
qctecmdr
ef242b391f Merge "disp: msm: dsi: trigger broadcast commands using DMA start window" 2020-12-07 17:09:16 -08:00
Sudarsan Ramesh
c6b636fe0b disp: msm: dp: validate edid before dereferencing
Currently, when using custom edid from debugfs, the
extensions data inside the edid block is not validated
before dereferencing the extension block.

The fix adds a edid validation function to validate
any custom edids before accessing any members in the
edid block.

Change-Id: I8a2cc45477416a8f8c4cff882bd53d14012e29f4
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
2020-12-07 10:02:42 -08:00
Yashwanth
d069726235 disp: msm: sde: update encoder atomic check during qsync usecase
During wb/cwb usecases, connectors_changed flag will be
set and needs modeset condition will be set to true. This
change updates qsync concurrency check with modeset to
fail atomic check only if there is seamless poms, dms or
dynamic clock scenario.

Change-Id: I1183f25cd45310fbd1d0b5ce67ee3d5dd3660fe0
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2020-12-07 16:15:23 +05:30
Sankeerth Billakanti
0386ae3a6b disp: msm: dp: handle link maintenance failures
Audio off is done before handling link maintenance
requests from sink or receiver. After handling the
link maintenance, audio is enabled without
verifying the success condition of the link
maintenance. If the link maintenance fails, then the
DP link will not be established and source will
not send video data. So, there is no need to
enable audio.

This change will skip the audio enable portion of
the code whenever the link maintenance fails. The
sink may eventually issue another irq_hpd to retry
the link training.

Change-Id: I1e9aab07d6465ab1b5e6f92717ef7288dc85068f
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
2020-12-07 00:07:54 -08:00
Sankeerth Billakanti
656690c02f disp: msm: dp: fix page fault from hdcp buffer access
There are certain cases where the start_auth and cleanup
are scheduled to be executed consecutively on the
sde_hdcp_2x_main thread. When this scenario occurs, the
functions to facilitate hdcp authentication which are
scheduled to execute after the clean needs to be protected
from dereferencing the freed hdcp message buffers.

This change will add a check to prevent dereferencing the
hdcp message buffer after hdcp cleanup is executed.

Change-Id: I669d25b7a6ce751127b1c21228b751eed8da5b38
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
2020-12-07 00:07:46 -08:00
Satya Rama Aditya Pinapala
fcb453c0b8 disp: msm: dsi: Add support for 5nm C-PHY shadow clock
Add support for 5nm DSI PLL C-PHY shadow clocks, which
will be used during dynamic dsi clock switch.

Change-Id: I55b11f2d0cffd8494d4641e9b2de0b88e7229978
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2020-12-05 08:33:29 -08:00
Satya Rama Aditya Pinapala
ae5b602b4f disp: msm: dsi: trigger broadcast commands using DMA start window
As per the HW requirements it is highly recommended to use DMA start
window to trigger  broadcast commands. If not used then it can
result in a hardware hang with the DSI controllers going out
of sync. This behavior is even more prominent in cases of higher
refresh rates. As part of the change we change the default DMA
scheduling behavior to default to maximum possible DMA window
in case it is not specified in the panel device tree.

Change-Id: Ied4df9063664cedbc18ce009054d4e5ecae30ab2
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2020-12-04 20:01:55 -08:00
qctecmdr
348e9b397c Merge "disp: msm: dp: remove debug log output in isr" 2020-12-03 22:53:43 -08:00