Maulik Shah
9bfdcbfcea
ARM: dts: msm: Update PSCI state id for shima
...
The wakeup value will be programmed by the secure firmware. This is
noted as the new E3 state for the RSC component.
Update state id for the AOSS sleep mode to pass new state.
Change-Id: I4c70bfa7f442e28a59d8809d2bd5afb6557de1d8
2020-09-15 15:44:53 +05:30
qctecmdr
520ea9a06c
Merge "ARM: dts: msm: Add trusted touch properties for shima"
2020-09-14 20:12:24 -07:00
qctecmdr
92e4ede673
Merge "ARM: dts: msm: Update GPU clock names for holi"
2020-09-14 20:12:24 -07:00
qctecmdr
780465bb41
Merge "ARM: dts: msm: Update QMP USB UNI PHY sequence for Lahaina to v0.96"
2020-09-14 20:12:24 -07:00
qctecmdr
5680b02a37
Merge "ARM: dts: msm: Add resources for Lahaina CC runtime_pm"
2020-09-14 17:26:14 -07:00
qctecmdr
ac3cd1500a
Merge "Revert "ARM: dts: msm: Add a two second polling for PMIC alarm in lahaina""
2020-09-14 17:26:14 -07:00
qctecmdr
f4970c1c34
Merge "ARM: dts: msm: Configure Policy engine for lahaina"
2020-09-14 17:26:14 -07:00
qctecmdr
e5d75e87ab
Merge "ARM: dts: msm: Update cnss dt node for bus bandwidth for shima"
2020-09-14 17:26:14 -07:00
qctecmdr
22464ef6f0
Merge "ARM: dts: msm: Add mpm counter node for boot_stats"
2020-09-14 06:19:35 -07:00
qctecmdr
910199eb64
Merge "ARM: dts: msm: Add GPU SMMU clocks for holi"
2020-09-14 06:19:34 -07:00
qctecmdr
5fba50fb1e
Merge "ARM: dts: msm: update DCVS node mapping table for shima target"
2020-09-14 06:19:34 -07:00
qctecmdr
2a90adaae5
Merge "ARM: dts: msm: Update the flags for GCC PCIE GDSC's"
2020-09-14 06:19:34 -07:00
Santosh Mardi
3a4a44c0e6
ARM: dts: msm: update DCVS node mapping table for shima target
...
Update DCVS node mapping table for L3 and ddr for shima target.
Change-Id: Id76c399c05b23895041c41ca533083928f644ebc
2020-09-14 02:31:24 -07:00
Jagadeesh Kona
4b471a8075
ARM: dts: msm: Update the flags for GCC PCIE GDSC's
...
Update the timeout and add flag to skip status check
on disable for PCIE GDSC's.
Change-Id: I560d9ba9986bb90ba07bf600464b44e4a580d0bd
2020-09-14 14:37:56 +05:30
Mayank Grover
3342752ca6
ARM: dts: msm: Add mpm counter node for boot_stats
...
Add mpm counter node to enable boot_stats collection
for holi.
Change-Id: I40962247765b07a7b62d3205b7c259ea36af020d
2020-09-14 00:52:44 -07:00
qctecmdr
29c2c0fbe7
Merge "bindings: clock: Add support for flag to stop bimc logging"
2020-09-14 00:22:42 -07:00
qctecmdr
8f15481fe4
Merge "ARM: dts: msm: Add support for BIMC stop logging for HOLI"
2020-09-14 00:22:42 -07:00
qctecmdr
683442c94f
Merge "ARM: dts: msm: Add reserved memory for dfps data region on Shima"
2020-09-14 00:22:42 -07:00
qctecmdr
61552f8b76
Merge "ARM: dts: msm: Include display panel for Trusted UI"
2020-09-14 00:22:41 -07:00
qctecmdr
05f3f31819
Merge "dt-bindings: add bindings for RIMPS memlat"
2020-09-14 00:22:41 -07:00
Ritesh Kumar
37d600e71e
ARM: dts: msm: Add trusted touch properties for shima
...
Add trusted touch properties to focaltech node to support
VM(virtual machine) enabled trusted touch on shima platform.
Change-Id: I7fa55db0905ab800e960981c6bd1fb7704f58dd6
2020-09-14 12:28:33 +05:30
Santosh Mardi
fac9cbdd40
dt-bindings: add bindings for RIMPS memlat
...
Add initial dt-bindings for RIMPS memlat and logging drivers.
Change-Id: I64a8cf4c77c4eb9c3333ac53ae603ef0ace3f0c8
2020-09-13 21:41:49 -07:00
qctecmdr
5797e93ad7
Merge "ARM: dts: msm: Add transaction timeout config for shima"
2020-09-13 21:34:17 -07:00
qctecmdr
da8bf20010
Merge "ARM: dts: msm: add osm register to minidump for shima"
2020-09-13 21:34:17 -07:00
qctecmdr
992b901e4f
Merge "ARM: dts: msm: Add EPSS hardware GT interrupts for SHIMA"
2020-09-13 21:34:17 -07:00
qctecmdr
8ee6d40e2d
Merge "ARM: dts: msm: Add llcc dcache dump nodes for shima"
2020-09-13 21:34:16 -07:00
qctecmdr
c7b76fb4ed
Merge "ARM: dts: msm: Enable smb1398 on holi MTP and QRD"
2020-09-13 21:34:16 -07:00
qctecmdr
f82e10852f
Merge "dt-bindings: Add support for GDSC flag to skip disable"
2020-09-13 21:34:16 -07:00
qctecmdr
2013a524dd
Merge "ARM: dts: msm: Enable CNSS PM domain support for Lahaina"
2020-09-13 16:08:29 -07:00
qctecmdr
42a949f2a4
Merge "dt-bindings: Add Dt binding for rimps mailbox"
2020-09-13 07:15:07 -07:00
qctecmdr
be4af8efe3
Merge "ARM: dts: msm: spss_utils: spss shared registers"
2020-09-13 07:15:07 -07:00
qctecmdr
411afea675
Merge "dt-bindings: iio: qcom,spmi-vadc: update prescale ratios"
2020-09-13 07:15:07 -07:00
qctecmdr
7671ab754b
Merge "dt-bindings: Add snapshot of qpnp-smblite documentation"
2020-09-13 01:13:30 -07:00
qctecmdr
63f3882bd4
Merge "ARM: dts: qcom: Update ACD control register values for A660v2"
2020-09-13 01:13:30 -07:00
Jishnu Prakash
bb9d9bc7d7
ARM: dts: msm: Enable smb1398 on holi MTP and QRD
...
Enable smb1398 master and slave charge pump nodes on holi
MTP and QRD.
Change-Id: Ib8bd88613ef69b18b344af5085d2d3269eb9bd38
2020-09-11 18:43:06 -07:00
qctecmdr
55110f1570
Merge "ARM: dts: msm: Correct name of tpdm ACTPM on holi"
2020-09-11 17:31:01 -07:00
qctecmdr
5ddc1a2a9f
Merge "ARM: dts: msm: Enable WLED for holi LCD platform"
2020-09-11 17:31:01 -07:00
qctecmdr
f9a3dd5166
Merge "ARM: dts: msm: Use a carveout for memshare memory"
2020-09-11 17:31:01 -07:00
qctecmdr
715c12898d
Merge "ARM: dts: msm: Add tzone-names for lahaina GPU"
2020-09-11 17:31:01 -07:00
Mohammed Mirza Mandayappurath Manzoor
0e3f40297c
ARM: dts: qcom: Update ACD control register values for A660v2
...
Update the dvm values for optimizing ACD performance and enable ACD
on lower levels.
Change-Id: I0031f5cbb0e19b132980951b4ff9abeff9204656
2020-09-11 14:35:53 -07:00
Ram Chandrasekar
71d7684d12
Revert "ARM: dts: msm: Add a two second polling for PMIC alarm in lahaina"
...
This reverts commit 9f163a1164
2020-09-11 14:35:31 -07:00
qctecmdr
67541e3c04
Merge "ARM: dts: msm: add haptics configuration for shima target"
2020-09-11 08:25:27 -07:00
qctecmdr
38cf9db931
Merge "ARM: dts: msm: Update PCIe1 PHY settings to v1.06 for lahaina"
2020-09-11 08:25:27 -07:00
qctecmdr
697a88b598
Merge "ARM: dts: msm: Update PCIe0 PHY settings to v1.01 for lahaina v2.1"
2020-09-11 08:25:16 -07:00
Hareesh Gundu
e125a33403
ARM: dts: msm: Add GPU SMMU clocks for holi
...
Add required GPU SMMU clocks for holi to avoid the
un-clocked register access from the gpu driver.
Change-Id: I3d46b26d8a0c1dc106aba675e9df26d48528001e
2020-09-11 19:39:50 +05:30
Tao,Zhang
7bde323c18
ARM: dts: msm: Add llcc dcache dump nodes for shima
...
Add llcc_1_dcache and llcc_2_dcache dump node to support these two
registers dump.
Change-Id: I7a390633f7b24bbce828104c85e4787019ba9206
2020-09-11 17:59:00 +08:00
Gaurav Kohli
78902b1136
dt-bindings: Add Dt binding for rimps mailbox
...
Adding rimps mailbox controller Dt binding.
Change-Id: I4b20b50f9a2d600affba29e518eaae28ad8e6275
2020-09-10 23:06:12 -07:00
Yuanfang Zhang
8ac529888a
ARM: dts: msm: Correct name of tpdm ACTPM on holi
...
The coresight TPDM name for ACTPM is spelled wrong as ACPTM, this
change fix this issue.
Change-Id: I0d5d6b3d40ac2b705a98a2b33ac49e7ccefc6bcf
2020-09-11 10:59:26 +08:00
Ram Chandrasekar
9f163a1164
ARM: dts: msm: Add a two second polling for PMIC alarm in lahaina
...
Add a two second polling for PMIC temperature alarm sensor to ensure the
software is in sync with hardware.
Change-Id: I5d0fc8eba6295b338252833581207d2ab189e33b
2020-09-10 15:48:42 -07:00
Isaac J. Manjarres
c3cdcaddc2
ARM: dts: msm: Use a carveout for memshare memory
...
The memshare driver currently uses CMA memory for its usecases. This
is problematic, as CMA memory has a normal cached mapping in the kernel,
which allows for speculative access. This makes it possible for a
speculative cache-line fill to occur, prior to the memory being unmapped
from the stage-2 page tables of Linux, as well as XPU protected. The
cache-line can later be evicted, while the memory is still XPU protected.
This results in a write to the system cache, which is blocked by the XPU,
resulting in an XPU violation.
Given the nature of the memshare usecases (i.e. the memory is allocated
once, and never given back to Linux), move the memshare driver to using
a carveout. Using a carveout makes it so that there are no normal cached
mappings in the kernel for the memory, which prevents speculative
cache-line fills from occurring.
Change-Id: I97e2fe144c8fde364ecd40fdd181a881ca93c4b1
2020-09-10 11:24:31 -07:00
