Some boards utilize several PMICs which contain clock divider
peripherals. Add support for the clock-output-names property
so that unique names can be specified for each divider clock.
If clock-output-names is not specified, then the clock names
will be div_clkN where N=1 to qcom,num-clkdivs.
Change-Id: I66b5fcd0a3890886fe1e8cd85b15ada8a55ecb0f
Signed-off-by: David Collins <collinsd@codeaurora.org>
clk_aop_qmp_prepare() is called from aop_qmp_clk_probe() before
devm_clk_register() is called. This means that clock hw->core
pointers are NULL and clk_hw_get_name(hw) triggers a NULL pointer
dereference. Use hw->init->name instead of clk_hw_get_name(hw)
to avoid the NULL pointer dereference.
Change-Id: I548df6518053260d44227adc0479b1ea52a81fc9
Signed-off-by: David Collins <collinsd@codeaurora.org>
Pass the mbox pointer to qmp_update_client() by reference so that
it is possible to update its value inside of the function.
Change-Id: Iefa4587f6e77b6e7029ed07236fa3a51ca09c129
Signed-off-by: David Collins <collinsd@codeaurora.org>
While registering the QDSS clock provider with the framework,
pass in the clk data array with references to both the QDSS
clocks. In its current implementation, the QDSS clock driver
only adds the clk_get callback for one of the clocks which
leads to clients getting the clock handle to it when they
try to reference either of the clocks.
Change-Id: I41fc4c1ea57ad0f59a1af126b6025c21af72cbe2
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Ensure that the clk-aop-qmp probe function correctly returns
-EPROBE_DEFER if mbox_request_channel() returns -EPROBE_DEFER.
This avoids invalid memory dereferencing during QDSS clock
calls in the case that the AOP mailbox is not yet available.
Change-Id: I4ef07ceaace05a1911f51992a181903b4365afe2
Signed-off-by: David Collins <collinsd@codeaurora.org>
Currently, duplicate enable requests are sent for the qdss_qmp_clk
during its registration. This is not ideal behavior and should be
corrected.
Change-Id: I1d66ad83fe9c109a88df527ef3fae5fc60e855e7
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
The Always On Processor(AOP) supports enabling, disabling and
scaling few shared clocks using the QMP mailbox client. Add
support for the same to register the QDSS clocks with AOP.
Change-Id: I31dd297acf639640a410494ad4dd96caa76a873f
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
The global mutex lock which was introduced to correct a droop issue on
certain devices during multiple enable/disable of GDSCs is no longer a
requirement, so remove the same to avoid the GDSC lock being acquired
while holding clock global lock causing the deadlock scenario.
Change-Id: Idc674dea06935509524afb89602599902dd03c56
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
There is no mandate in hardware that the SW_COLLAPSE bit of the
GDSC be cleared while disabling its hardware control. Remove the
polling logic to check whether the GDSC is enabled via the SW
vote on clearing the HW_CONTROL bit.
Change-Id: Ib08b627a3502d1096ae7d05ef077a50b95fc80d2
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Refactor the gdsc_probe() function to reduce its cyclomatic
complexity. This helps to make the gdsc-regulator driver easier
to understand and maintain.
Change-Id: I285c01a6cca7609bb09ef0c769db5bde8dc142a6
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for the RETAIN_FF_ENABLE feature which enables the
usage of retention registers. These registers maintain their
state after disabling and re-enabling a GDSC.
Change-Id: Iad19bfb2cb73fa76aad230bad6372d68b447b4e2
Signed-off-by: David Collins <collinsd@codeaurora.org>
When clients call the regulator_is_enabled() API for GDSCs that
are sourced off of the MMCX rail, any register accesses that will
be made as part of the callback rely on the presumption that the
MMCX rail is enabled. When the rail is disabled, the corresponding
ahb clocks that are needed for these registers to be accessible
will also be turned off, thus leading to an unclocked access. Check
to make sure that the MMCX rail is enabled prior to reading or
writing to the MM registers.
Along similar lines, add logic to enable the parent rail for the
GDSC prior to reading and writing to the GDSC registers during the
set_mode and get_mode callbacks.
Change-Id: I8265bc147efd2acd1d6638638eb78935762feee8
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
For GDSCs that reside on domains that are collapsible and
support a minimum voltage of retention, explicitly vote on
the minimal operating voltage, LowSVS for the rail. This is
required as an interim step before enabling/disabling the
GDSC. Once that's done and the GDSC has latched on to its
new state, remove this voltage vote.
Note that this fix-up patch has been squashed in:
commit c7d3dc884292 ("clk: qcom: gdsc: Fix issue with
dereferencing NULL pointer in gdsc APIs").
Change-Id: Ibac43bba8248d68f8355d1a9db9cfcbfb9fa7557
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
[collinsd@codeaurora.org: squashed in a fix-up patch]
Signed-off-by: David Collins <collinsd@codeaurora.org>
Support globally distributed switch controller(GDSC) devices as
regulators. This will enable clients to use the regulator framework
APIs to enable/disable the GDSCs.
The hw_ctrl/domain_ctrl registers which might be required to be
enabled before the GDSC are modelled using syscon framework.
Change-Id: I2d63105d032ab16d5555722680f4371c831823cd
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
[collinsd@codeaurora.org: removed clk_set_flags() calls]
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add new ops to allow clock clients to enable/disable hardware
dynamic gating of the clock branch.
Change-Id: I14abed3827de8cefc31f3deb3c1e589136c32b8d
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
Currently, if clk_set_rate() is called on a disabled clock that
has flags = FORCE_ENABLE_RCG, the rate is neither physically set
nor properly cached in software. This means that when the clock
is later enabled, its rate will not be what was previously
requested.
Change the handling of FORCE_ENABLE_RCG so that all clk_set_rate()
calls are respected regardless of a clock's enable state. In
doing so, ensure that FORCE_ENABLE_RCG and enable_safe_config are
supported both individually and together.
Implement the following behavior:
enable_safe_config == true:
enable - configure the RCG according to the cached current_freq
disable - configure the RCG for CXO (safe) source
set_rate - (if prepared) configure the RCG for the requested rate
(if not prepared) cache the rate in current_freq
flags | FORCE_ENABLE_RCG:
enable - set ROOT_EN=1 to force the RCG to be enabled
disable - set ROOT_EN=0
set_rate - configure the RCG for the requested rate;
if disabled, then set ROOT_EN=1 before the
configuration is changed and ROOT_EN=0 after
enable_safe_config && (flags | FORCE_ENABLE_RCG):
enable - set ROOT_EN=1 and configure the RCG according to the
cached current_freq
disable - configure the RCG for CXO source and set ROOT_EN=0
set_rate - (if prepared) configure the RCG for the requested rate
(if not prepared) cache the rate in current_freq
Change-Id: Ib7442e4a4b572ae7c567929044410e09a9886c76
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add a flag to indicate to support and enable hardware control mode
of an RCG.
Change-Id: I21194a463441ea13b7575a4174b1f96504b42b1e
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The commit 7533b7fb5495 ("clk: qcom: clk-rcg2: Read RCG source before
calculating clk rate")' had introduced a function to update the src map,
but there could be a race where a set_rate for a clock from a particular
CC on a CPU could override the global cxo_f which was set by clock
enable/disable for a clock from another CC.
Change-Id: Id86818895e226a387e7fd1a09e2034eee18fd361
Signed-off-by: Taniya Das <tdas@codeaurora.org>
If the clock rate is set previously to hlos and enable
safe config is true. In that case we need to check the
rcg source to make sure recalc will return correct rate.
Rate calculation is done based on selected source rather
than 19.2 MHZ. Also, we are setting correct src value for
XO based on the parent map of a particular clock.
Change-Id: Id6d2923136a0848d55cff37fb5ef2e3b092af27a
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
There could be cases where a simultaneous clk_disable and clk_set_rate on
the same rcg could result in a wrong recalc rate. So for shared rcgs
get the pre_div value based on the current frequency from the frequency
table.
Change-Id: Ia5730e43965b2d0ba19da05fca47825514f98865
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The Alpha BW for Fabia PLL is 16 bit and the calculated hw rate has
additional KHz of frequency. Due to this additional frequency, the
source is wrongly selected. Truncate the additional KHz using the
DIV_ROUND_CLOSEST_ULL.
Change-Id: Ic9c523c87277c4813b676cf8a52a1207e8f1ecc2
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
Add null pointer checks for the parent clock pointers returned
by clk_hw_get_parent() and clk_hw_get_parent_by_index() in
several qcom clock drivers.
Change-Id: I869c9e35b7ec083b34bcc70d18601aec64c3ac97
Signed-off-by: David Collins <collinsd@codeaurora.org>
Move reading of MN counter mode register earlier to source sel
to fix overwrite of MN counter mode variable.
Change-Id: I5a318112e85c4af83fdbf9bba8770f4ec1b84326
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Update the DEFINE_RCG_DFS() macro to avoid the potential clock
struct name aliasing.
This modification originally came from:
commit c88b8062898c ("clk: qcom: Add cdiv clocks for gcc, video
and camera cc driver for KONA").
Change-Id: I5a8b694b5b8a8b5169639a3e09b1ab4c1936e010
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add clock ops for taking care of a dependent clock when the actual
clock requests are made.
Change-Id: I52691ef9f183da035ddf9c05fb73811f48fef74c
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
Fix certain functions with potential for a NULL
pointer de-reference.
Change-Id: I855ef1d883a22616db7086bd5d47ee1f8e54694a
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add new RCG clock ops specific for the DP clock source.
Change-Id: I2ec5ddcfd47af8362f76d76d153e30d4e2f45370
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Some RCGs could have sources with dynamic frequencies and fixed sources
where if the RCG has the flag of CLK_SET_RATE_PARENT set, it would try to
propagate the clock rate to the fixed source PLLs too. To identify sources
of the RCGs where the rate should propagate to parent PLL, add a member in
freq_tbl to represent source frequency. This would be used by the
_freq_tbl_determine_rate to set its parent frequency on the PLL.
Change-Id: I7f1c0d9d84607821893a1e5d17934dae5acef5f4
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
In certain cases, it is desirable for an RCG to be turned on
explicitly instead of just relying on the enable signal from
its branch clock(s). Add support for this.
Change-Id: I2b0b81bddfe7cc7543c313e4ed13a332fb1a0fcb
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
In certain cases, an RCG might be prone to being enabled even
though the overlying software thinks that it disabled the RCG.
In order to avoid letting the RCG go into an invalid state, support
parking it at a safe frequency during clk_disable() and deferring
all the RCG configuration updates to be done during clk_enable(),
if a scaling request comes in whilst the clock is disabled.
Change-Id: I55f1d1d346182a2b480127c57d6659fc9a63331b
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
The sequence for alpha_pll_lucid_prepare is checking an incorrect bit
to determine whether or not a lucid PLL has calibrated successfully.
The bit in the status register is not observable unless pll_test_ctl[69]
is set and user_ctl[43:37] is 0 which should only be used as a fallback
option. Use the correct PCAL_DONE bit from the mode register to properly
determine PLL calibration status.
Change-Id: If952c30cacacd68c07e8d7dfd622069dbb70c909
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Some instances of the Zonda PLL do not lock correctly
in high L-VAL regions. In such cases, CFA mode
can be configured via test_ctl_val to use an alternative
locking mechanism. Add support for CFA mode by
polling FREQ_LOCK_DET instead of PLL_DET_LOCK
whenever CFA mode has been configured.
Change-Id: Ief31592250ea9f329a34ffdbc4b17cfce431677d
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
There are different configurations of display panels which may
or may not enable display PLLs before the display driver probes. Due to
continuous splash use cases, we may trample over existing PLL
configuration and cause the PLL to reset while it's in use. Prevent that
scenario by skipping the PLL configuration step if it's enabled.
Change-Id: I61f69c67ca57f18cbc6b551884ea199212ed4e9d
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Under some circumstances, such as during subsystem restart, the
registers for a clock controller may be reset to hardware default
values. Add support to reconfigure a Lucid PLL during clk_prepare
in the case that the CAL_L_VAL is found to be 0 before performing
calibration.
Change-Id: Idef3c42dfb32748ec40f89a9dab9f6ab86e293f6
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for configuring custom target-specific registers
during PLL initialization.
Change-Id: Id296ae904d1b74e7c2f90027bd557bdc62b1d362
Signed-off-by: David Collins <collinsd@codeaurora.org>
Remove reconfiguration of PLLs as configuration is expected
to be one time that is during probe.
Change-Id: I90f8ed553016ab32786beae0873424579ead564d
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Zonda PLL is high frequency PLL clock generator. It supports
fine control of the digital controlled oscillator (DCO)
and clocked on rising edge of the reference.
Change-Id: I2a9726a0acbffcee1a52f5172b197bf125e60030
Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support to configure test_ctl, user_ctl and cal_l fields for PLLs.
Change-Id: Ib5a7a74aecd8d9885e0a3034f097c13cda4d2268
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Add programming sequence support for managing the Lucid
PLLs.
Change-Id: Ia63067d88bd1f309d190b1ec5b0f272b40209a71
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: David Collins <collinsd@codeaurora.org>
Enable RSC controller driver to be compiled as modules. Since RPMH
communication is need for enabling/disabling critical clocks and busses
needed for the application processor, it is better to keep this module
enabled. Hence declare the driver as a builtin platform driver.
Change-Id: I41a657c0d618efb7c3460833ffb8eb5d445885a0
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Add support to dump command DB data via debugfs. This allows drivers to
lookup data resource information without a resource ID.
Updated to use leXX_to_cpu() functions when reading cmdDB memory.
Change-Id: I04e7466f76ceea00d762752e0c0123edfabe0f64
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
llcc supports 2 memory controllers in backend on certain systems.
This patch adds support for dual memory controllers. Also fixed
filter related changes in LLCC. Cleaned up the code for better
code walk.
Change-Id: Ie054d9182b20ec0811f117c2289aa857f0384baf
Signed-off-by: Avinash Philip <avinashp@codeaurora.org>
This is snapshot of the llcc_perfmon driver from msm-4.14
'commit c9961d61d6d8 ("drivers: soc: llcc_perfmon: Add llcc_perfmon
support")'
This LLCC perfmon driver provides Sysfs interfaces for the clients to
monitor the events. Driver support for monitor events from LLCC sub blocks.
Also updated driver to handle opcode & cache alloc filters.
Change-Id: Ic711fdbc774d2da1938feff5c0d7888e5cf8495a
Signed-off-by: Sankaran Nampoothiri <snampoot@codeaurora.org>
Signed-off-by: Avinash Philip <avinashp@codeaurora.org>
This is a snapshot of cnss_prealloc driver and associated files as of
msm-4.19 commit 94d53f998edd
("cnss_prealloc: Update prealloc memory table").
Change-Id: Ic6e853bf651e2a0e2b672bc68d42929c3b55ef93
CRs-Fixed: 2500800
Signed-off-by: Yuanyuan Liu <yuanliu@codeaurora.org>
