Commit graph

893,658 commits

Author SHA1 Message Date
qctecmdr
d6880ae4e7 Merge "regulator: qpnp-lcdb: Add support for NCP symmetry with LDO" 2021-01-26 22:58:58 -08:00
qctecmdr
95f9eaf581 Merge "clk: qcom: Add GPU clock driver for SM6150" 2021-01-26 22:58:57 -08:00
qctecmdr
676add9521 Merge "defconfig: quinvmauto: Enable virtio i2c" 2021-01-26 19:23:22 -08:00
qctecmdr
b9fd98cf56 Merge "Merge android11-5.4.61+ (5327444) into msm-5.4" 2021-01-26 09:17:59 -08:00
Veera Vegivada
dcf1d44e01 clk: qcom: Add GPU clock driver for SM6150
Add support for the graphics clock controller found on SM6150
based devices. This should allow GPU device drivers to probe
and control their clocks.

Change-Id: Ic4dc10771a4ea79d181be38e6f1594ecc6f314d3
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2021-01-26 15:20:03 +05:30
Veera Vegivada
0c8678736a clk: qcom: Add display clock driver for SM6150
Add support for display clock controller found on SM6150
based devices. This would allow display device driver
to probe and control their clocks.

Change-Id: I2e5e20f5bf518d6bc1128b6c2fb26a5e0480a4a3
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2021-01-26 15:19:22 +05:30
Veera Vegivada
f7a5ea0098 clk: qcom: Add camera clock driver for SM6150
Add support for camera clock controller found on SM6150
based devices. This would allow camera device drivers
to probe and control their clocks.

Change-Id: Ic5b5e6e9363f0272e777c500028f876f3e79a7b8
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2021-01-26 15:18:42 +05:30
Veera Vegivada
4081ddd99b clk: qcom: Add GCC clock driver for SM6150
Add support for peripheral clocks controlled by
global clock controller.

Change-Id: I7717b8e32fd3918359faf3d63af2f6a82de81088
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2021-01-26 15:18:02 +05:30
Veera Vegivada
4757acd396 clk: qcom: rpmh: Add support for RPMH clocks for SM6150
Add clock rpmh data to communicate with RPMH clocks for SM6150.

Change-Id: I6aed48fce932923e52dc9109cca427da92375814
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2021-01-26 15:17:00 +05:30
qctecmdr
58fb72eeee Merge "sched/walt: Improve the scheduler" 2021-01-26 01:04:10 -08:00
Zhiqiang Tu
8163d656ac defconfig: quinvmauto: Enable virtio i2c
Enable virtio i2c driver for quinvmauto target.

Change-Id: I2c4591a7620ad52332b7fdfe5d53d0605628c98f
Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
2021-01-26 16:53:27 +08:00
qctecmdr
74cf4c88c8 Merge "msm: ipa: header file to support wdi 2.4G new pipe" 2021-01-25 17:09:08 -08:00
qctecmdr
fe550d926f Merge "defconfig: enable qdss component for sdxnightjar" 2021-01-25 17:09:07 -08:00
qctecmdr
40fdf3ea74 Merge "arm64: defconfig: Enable UFS controller for SA6155" 2021-01-25 13:33:31 -08:00
qctecmdr
c39fd549d3 Merge "power: smb1398: Replace use of do_div() with plain division" 2021-01-25 13:33:30 -08:00
qctecmdr
b0fec7e6e2 Merge "usb: f_gsi: Increase ADPL buffer depth to 30" 2021-01-25 06:19:18 -08:00
qctecmdr
2b4e0cfccf Merge "defconfig: gen3auto: Enable QFPROM driver" 2021-01-25 06:19:18 -08:00
qctecmdr
3e2b3819e6 Merge "cnss2: Dump mhi debug registers on receiving mhi WAKE event cb" 2021-01-25 06:19:18 -08:00
Pavankumar Kondeti
a0f963c162 sched/walt: Improve the scheduler
This change is for general scheduler improvement.

Change-Id: I288fc9a8858cb29ae9c6993b398a349b4a8c7475
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
2021-01-25 19:02:41 +05:30
Veera Vegivada
e3418144c0 arm64: defconfig: Enable UFS controller for SA6155
Add support for UFS controller.

Change-Id: I39feb91b5f2e635d27a751c33bb07a703133debb
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2021-01-25 18:33:56 +05:30
Veera Vegivada
ede1f0a6db arm64: sdmsteppeauto: Enable OSM L3 interconnect driver
Enable OSM L3 interconnect driver so that consumers
can change the hardware state based on the usecase.

Change-Id: Ibb4156ff5adbf5c874951e781f41706828fa5751
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2021-01-25 18:31:30 +05:30
Veera Vegivada
84abd630f7 arm64: defconfig: Enable SM6150 interconnect driver
Enable the SM6150 interconnect driver so that consumers are
able to obtain their path handles properly.

Change-Id: Ie6b99d37f73b69dc375426d64e9148b9a64180f5
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2021-01-25 18:29:48 +05:30
qctecmdr
c8429d64fc Merge "cnss2: Add code to download qdss trace config" 2021-01-25 02:40:21 -08:00
qctecmdr
fb50822968 Merge "qseecom : Add support for fuse syscall" 2021-01-25 02:40:21 -08:00
qctecmdr
e92b33876b Merge "msm: kgsl: Enable some essential features for A680 GPU" 2021-01-25 02:40:21 -08:00
qctecmdr
5276cb9926 Merge "cnss2: Update GPIOs for wake capability disablement" 2021-01-25 02:40:20 -08:00
Jishnu Prakash
de7005f054 regulator: qpnp-lcdb: Add support for NCP symmetry with LDO
Add a device tree property which enables NCP symmetry. This
configuration in HW enables the NCP voltage to follow LDO.

Change-Id: If44b049a3ecd031f111dcb8477166925a0d01914
Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
2021-01-25 14:30:06 +05:30
Zhiqiang Tu
2202e76aae defconfig: gen3auto: Enable QFPROM driver
Enable QFPROM to support NVMEM read/write.

Change-Id: I54dbc765a24b163f4cdb2f658a21ad95d842314f
Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
2021-01-24 23:46:01 -08:00
Yuanfang Zhang
59d75f4711 defconfig: enable qdss component for sdxnightjar
Enable qdss component ETM/STM/CTI/TPDM/TPDA/TMC on sdxnightjar.

Change-Id: I147b1078c7a524d9366cd769019461b344a1cfc7
Signed-off-by: Yuanfang Zhang <zhangyuanfang@codeaurora.org>
2021-01-25 15:33:17 +08:00
qctecmdr
52da8f55ee Merge "msm: kgsl: Add enable_signaling for timeline fence" 2021-01-24 22:54:19 -08:00
qctecmdr
cbef52ce19 Merge "power: smb358: Add support to make SMB358 driver GKI complaint" 2021-01-24 22:54:19 -08:00
Monika Singh
d9858f6b11 qseecom : Add support for fuse syscall
Add changes to support syscall to return fuse
configuration on the device. Also rename
function to improve redability.

Change-Id: Idec01fec75a5dd6a86ad6dc319d18129c4ec2740
Signed-off-by: Monika Singh <monising@codeaurora.org>
2021-01-25 10:42:24 +05:30
Hui Li
49644357e0 msm: kgsl: Enable some essential features for A680 GPU
Enable PREEMPTION, IFPC, CONTENT_PROTECT, IOCOHERENT
supports for sdmshrike platform.

Change-Id: I8238c4ac7fff6c607b0eafb9fdfab13cdf44003f
Signed-off-by: Hui Li <hul@codeaurora.org>
2021-01-24 19:39:11 -08:00
Zhiqiang Tu
f9bd900b8a i2c: virtio: Add snapshot of virtio i2c driver
Add snapshot of virtio i2c driver from msm-4.14.
This snapshot is taken as of msm-4.14 commit 972d72613cd1
("i2c: virtio: Fix return value issue of transfer function").

Change-Id: Idb4f6b5918f7d7237146d02839638b8a97a05c02
Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
2021-01-24 05:11:10 -08:00
qctecmdr
e168b52f6b Merge "msm: pcie: Add tcsr configuration" 2021-01-23 23:36:22 -08:00
qctecmdr
b368317cea Merge "clk: qcom: gpucc-yupik: Remove GPUCC PLL0 configuration from HLOS" 2021-01-23 23:36:22 -08:00
Hardik Kantilal Patel
2273a9e6c9 ICNSS2: Enable Runtime PM feature for Moselle
Enable Runtime PM feature for Moselle.

Change-Id: I210a77052a25067802ca74eb82ad2a045d4c7dbc
Signed-off-by: Hardik Kantilal Patel <hkpatel@codeaurora.org>
2021-01-23 19:08:33 +05:30
qctecmdr
c522f59658 Merge "iommu/arm-smmu: Fix SMR mask extraction for bootloader programmed SMRs" 2021-01-22 21:12:24 -08:00
qctecmdr
22e7b8f5e9 Merge "msm: pcie-ep: Use default PCIe CLKREQ# settings" 2021-01-22 21:12:24 -08:00
qctecmdr
8349627940 Merge "msm: cvp: Support handling cp camera buffer" 2021-01-22 17:31:16 -08:00
qctecmdr
ccffb23bfa Merge "msm: kgsl: Enable Preemption on A635 GPU" 2021-01-22 17:31:16 -08:00
qctecmdr
4d6ec09334 Merge "defconfig: Configure MaxPower to 900mA" 2021-01-22 17:31:15 -08:00
Isaac J. Manjarres
8b27d2333a iommu/arm-smmu: Fix SMR mask extraction for bootloader programmed SMRs
When extracting the mask for an SMR that was programmed by the
bootloader, the SMR.valid field is also extracted and is treated
as part of the mask. This causes issues when removing an SMMU
master, as removing the master involves constructing an SMR
entry with the mask and SID without the valid bit set and writing
that value to the SMR. However, since the valid bit was part of
the mask, the SMR will still be valid.

Instead, remove the valid bit from the raw SMR value that is used
for extracting the SMR mask.

Change-Id: Iccada2c474b196200ae1b56eb9faa9cb026f5ef1
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2021-01-22 15:41:13 -08:00
Siddartha Mohanadoss
7328656346 msm: pcie-ep: Use default PCIe CLKREQ# settings
Use default settings for CLKREQ# from pinctrl DTSI.
Configuring the GPIO in the HLOS driver is causing the
PCIe controller to go down and any DBI access is causing
a NOC error. Since this GPIO is not configured during
resume or sleep the driver can rely on the pinctrl settings
that is programmed as part of the TLMM driver initialization
of the GPIO as default.

Change-Id: Ib6a62e6aa471c39858302fdc0e575fc7ab5abff4
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
2021-01-22 15:33:35 -08:00
qctecmdr
78bb563bf8 Merge "input: qcom-hv-haptics: check playing effect pointer in IRQ handler" 2021-01-22 13:46:45 -08:00
qctecmdr
c1cc7c0229 Merge "usb: core: Reduce resume signalling time for devices behind external hub" 2021-01-22 13:46:44 -08:00
qctecmdr
e9b58393fb Merge "pinctrl: qcom: Expose ufs_reset as gpio on sm6150" 2021-01-22 13:46:44 -08:00
qctecmdr
6bfe888368 Merge "defconfig: Add configs to enable cpufreq/devfreq" 2021-01-22 13:46:44 -08:00
qctecmdr
63121c3d1e Merge "defconfig: gen3auto: Enable QCOM_SCM" 2021-01-22 13:46:44 -08:00
qctecmdr
a8e20ab52c Merge "defconfig: quinvmauto: Enable hab and peripheral drivers" 2021-01-22 13:46:43 -08:00