Commit graph

893,891 commits

Author SHA1 Message Date
qctecmdr
d6e5dbfa66 Merge "cnss2: Increase QMI and MHI timeouts for emulation builds" 2021-02-10 21:04:14 -08:00
qctecmdr
99b05f75d7 Merge "cnss2: Update board data file name for certain RF chip ID" 2021-02-10 21:04:14 -08:00
qctecmdr
3764089c41 Merge "Revert "pci: msm: msm_pcie_iatu_config API clean"" 2021-02-10 21:04:13 -08:00
qctecmdr
8788af123f Merge "sched/walt: Remove weak symbols" 2021-02-10 21:04:13 -08:00
qctecmdr
a97a28d8ac Merge "msm: kgsl: Fix adreno_cmdbatch_retired tracepoint format" 2021-02-10 17:26:20 -08:00
qctecmdr
4a442b681f Merge "defconfig: Enable Socinfo and gpio sysfs for monaco" 2021-02-10 17:26:20 -08:00
qctecmdr
15525bb9b4 Merge "usb: gsi: Retry USB function wakeup if USB is into low power mode" 2021-02-10 17:26:19 -08:00
qctecmdr
8c903957bf Merge "Fallback to dma_alloc_coherent if shmbridge is disabled" 2021-02-10 12:32:17 -08:00
qctecmdr
bd060db274 Merge "msm: mhi_dev: Redesign UCI transfer request structure management" 2021-02-10 12:32:17 -08:00
qctecmdr
06a569ccf0 Merge "usb: f_cdev: Retry USB function wakeup if USB is into low power mode" 2021-02-10 12:32:17 -08:00
Yue Ma
2c7f9aa572 cnss2: Increase QMI and MHI timeouts for emulation builds
Increase QMI and MHI default timeouts for emulation builds. Also
set timeout for MHI power on as multiple default timeout value
instead of a fixed number so that it can be changed at runtime
for debug purpose.

Change-Id: I483a458f54083644f9acd2a484243016901c4776
Signed-off-by: Yue Ma <yuem@codeaurora.org>
2021-02-10 10:30:15 -08:00
Hemant Kumar
7d060f0e12 Revert "pci: msm: msm_pcie_iatu_config API clean"
This reverts commit b9b4ade986.
Older ver of SNPS core needs viewport registers as it does not
have separate iATU region. Hence keep the viewport support.

Change-Id: Ic863eb3332c54df433726064591a01dc50d29565
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
2021-02-10 10:15:09 -08:00
Yue Ma
537b4dfdef cnss2: Update board data file name for certain RF chip ID
If higher 4 bits of chip ID (device major version) is 1, read board
data file name as bdwlang.e<board ID>. The assumption is board ID
will be always less than 0xFF. If board ID (0xFF) is invalid in OTP
then read it as bdwlang.elf for such case. Also only use lower 4 bits
of device major version as the version number to load firmware file
because of above new requirement.

Change-Id: I4dce528a9c389a660b19dabe4ee44e655a23570b
Signed-off-by: Yue Ma <yuem@codeaurora.org>
2021-02-10 09:52:59 -08:00
Pavankumar Kondeti
ed709b862b sched/walt: Remove weak symbols
The weak symbols are no longer needed as the WALT code is
moved from techpack to kernel.

Change-Id: I2918ac475d264482b039ee8b65357657c427eb28
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
2021-02-10 17:06:11 +05:30
Pavankumar Kondeti
40119a104b sched/walt: sched: Improve the scheduler
This change is for general scheduler improvemnts.

Change-Id: If28d00691bc42b62cc4fc96a49d601c7ac5e3e34
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
2021-02-10 17:06:11 +05:30
qctecmdr
d03a80d9e6 Merge "cnss2: Add WLAN device OTP version debug print" 2021-02-10 03:35:48 -08:00
qctecmdr
d29dae0d9e Merge "drivers: edac: Add support to re-enable edac on cpu hotplug" 2021-02-10 03:35:47 -08:00
qctecmdr
ee54228ff1 Merge "defconfig: gen3auto: enable PCA954x & SX150X driver for sa8155/sa8195" 2021-02-10 03:35:47 -08:00
qctecmdr
45e50c18be Merge "dt-binding: clock: add 7nm/14nm display pll headers for Gen3" 2021-02-10 03:35:47 -08:00
qctecmdr
c589225bc3 Merge "msm: kgsl: Avoid slumber if interrupt is pending" 2021-02-10 03:35:46 -08:00
qctecmdr
775a0853af Merge "msm: pci: Update VREG info fron DT" 2021-02-10 03:35:45 -08:00
Zhiqiang Liu
676d6f86bb dt-binding: clock: add 7nm/14nm display pll headers for Gen3
Add 7nm/14nm display pll clock headers for Gen3 platforms.

Change-Id: I5b77a9d8d243eca25264fabbee12207c374908cc
Signed-off-by: Zhiqiang Liu <zhiqliu@codeaurora.org>
2021-02-08 13:44:50 -08:00
qctecmdr
db5f5ed622 Merge "sched/walt: Move scheduler techpack to kernel" 2021-02-07 22:42:28 -08:00
qctecmdr
14507f613f Merge "cnss2: Use CONFIG_PCI_MSM to protect MSM PCIe APIs" 2021-02-07 22:42:28 -08:00
qctecmdr
0667a1b5dc Merge "usb: dwc3: Issue ENDTRANSFER cmd on ep0 unconditionally" 2021-02-07 15:30:41 -08:00
qctecmdr
b80f916238 Merge "drivers: soc: qcom: rimps_memlat: check cpu in idle path" 2021-02-07 11:45:28 -08:00
qctecmdr
aeeaa66033 Merge "input: touchscreen: focaltech: use proper dev" 2021-02-07 11:45:27 -08:00
qctecmdr
baeb717e11 Merge "net: cnss: add snapshot of cnss platform driver" 2021-02-07 11:45:27 -08:00
qctecmdr
5b34e22e77 Merge "usb: phy: qusb: Use scm call to update LVL_SHIFTER register" 2021-02-07 11:45:26 -08:00
qctecmdr
c1813e9149 Merge "cnss2: Update qdss config file name" 2021-02-07 11:45:26 -08:00
Nagireddy Annem
013b2bbb1b defconfig: Enable Socinfo and gpio sysfs for monaco
Enable Socinfo and GPIO sysfs configs for monaco.

Change-Id: I45a45fbbae2dac3e558dc3cb9e8f33b734187efd
Signed-off-by: Nagireddy Annem <nannem@codeaurora.org>
2021-02-07 05:16:24 -08:00
qctecmdr
86401a1787 Merge "arm64: defconfig: enable qcom_scm/fastscvp on gen3auto" 2021-02-06 22:12:47 -08:00
qctecmdr
238b1e37b4 Merge "perf: Add exclude_idle support for armv7 PMU" 2021-02-06 05:10:46 -08:00
qctecmdr
68fd89baf1 Merge "leds: leds-qti-tri-led: Don't print error log for -EPROBE_DEFER" 2021-02-06 05:10:46 -08:00
qctecmdr
9e93c40032 Merge "usb: phy: snps: Ensure SIDDQ is disabled for proper functioning" 2021-02-06 05:10:46 -08:00
qctecmdr
46bb8e6b35 Merge "pinctrl: add restore function for sx150x" 2021-02-06 05:10:45 -08:00
qctecmdr
ac5c618ac5 Merge "net: qrtr: fix tx flow memory leak" 2021-02-06 05:10:45 -08:00
qctecmdr
dc655ccb0e Merge "soc: qcom: Reset watchdog before setting bite time" 2021-02-06 05:10:44 -08:00
qctecmdr
fec650e1be Merge "cnss2: Fix error case print for dev_boot debugfs" 2021-02-06 05:10:44 -08:00
Laisheng Hu
6152c18649 arm64: defconfig: enable qcom_scm/fastscvp on gen3auto
enable qcom_scm and fastcvpd for vidc driver.

Change-Id: Idb17a079e1472e1d2a853d2ea68da6933768d7e1
Signed-off-by: Laisheng Hu <laisheng@codeaurora.org>
2021-02-06 04:33:58 -08:00
Pratham Pratap
42a90ced12 usb: dwc3: Issue ENDTRANSFER cmd on ep0 unconditionally
Consider a case where ep0 is not in setup stage and composition
switch happens. Currently DWC3_DEPCMD_ENDTRANSFER command is not
issued on ep0 which means that the transfers are not flushed out
and driver clears the run/stop bit hence stopping the controller.
Now as soon as driver sets the run/stop bit controller tries to
access the trb from the previous session which is already unmapped
resulting in SMMU fault.

Fix this by unconditionally issuing DWC3_DEPCMD_ENDTRANSFER
command on ep0. Although it is not specified in the data book
but if we know for sure that we are anyway going to stop the
controller then we can issue ENDTRANSFER command on ep0.

Change-Id: Ic6ee570acc8926897d3b6042181a501a47438d92
Signed-off-by: Pratham Pratap <prathampratap@codeaurora.org>
2021-02-05 22:31:13 -08:00
qctecmdr
9a855e1c71 Merge "pci: switch: Add snapshot of PCIe switch driver" 2021-02-05 18:01:29 -08:00
qctecmdr
47d8e027d9 Merge "usb: dwc3: core: Select UTMI clock before core_soft_reset" 2021-02-05 18:01:28 -08:00
qctecmdr
64f86ae513 Merge "pci: msm: msm_pcie_iatu_config API clean" 2021-02-05 18:01:28 -08:00
qctecmdr
9d0e285207 Merge "msm: pcie: provide client the ability to control PCIe target_link_speed" 2021-02-05 18:01:28 -08:00
qctecmdr
d8ba3161ed Merge "cnss2: Add support for PCI wake GPIO" 2021-02-05 18:01:27 -08:00
Yue Ma
2dc22bc62d cnss2: Use CONFIG_PCI_MSM to protect MSM PCIe APIs
This can ease the complexity to port CNSS2 driver to non-MSM
platforms while still be able to maintain the compatibility.

Change-Id: I268cdd90c59085b34aa2fe3c3b845d60c4e2a417
Signed-off-by: Yue Ma <yuem@codeaurora.org>
2021-02-05 17:31:07 -08:00
Yue Ma
dc0ecaca75 cnss2: Set initial target PCIe link speed to Gen2 for QCA6490
Since there may be link issues if QCA6490 device boots up with Gen3
link speed, always set initial target PCIe link speed to Gen2. Device
is able to change it (back) later at any time if needed.

Change-Id: I9d617d71926fe98e59e67aff772984878e0a2689
Signed-off-by: Yue Ma <yuem@codeaurora.org>
2021-02-05 17:30:27 -08:00
Dennis Cagle
878506879e defconfig: sdxlemur: Remove slub debug config
Remove CONFIG_SLUB_DEBUG_ON from debug variant for performance
reasons. Also remove redundant HARDENED_USERCOPY from debug config
since this gets copied over from the standard config.

Change-Id: I7c6fc8620290cf126ced046f82811e9e39bc2a60
Signed-off-by: Dennis Cagle <dcagle@codeaurora.org>
2021-02-05 14:35:31 -08:00
Tony Truong
d0cb56ec45 msm: pcie: provide client the ability to control PCIe target_link_speed
There are usecases where clients want to change the maximum GEN
speed that PCIe can link up with. Provide clients the ability to
control the maximum PCIe GEN speed to for such usecases.

Change-Id: I834bee2063133546c9b0ebac2d5328ffbc5ceac6
Signed-off-by: Tony Truong <truong@codeaurora.org>
2021-02-05 12:54:14 -08:00