This change will add all the power sources which are needed
for automotive BT SoCs QCA6574/QCA6595/QCA6696.
Change-Id: Icaa9d6fe9d8fc8f51a23caeaa6dd950757b6c7ef
Signed-off-by: Xiaoning Ma <mxiaonin@codeaurora.org>
The trustzone will write apps stats into smem. This change
adds support to read and display it when rpmh_unit_base is
not present.
Change-Id: Ifc3566018fd6722eb2d818d8d81370dc1f8cea19
Signed-off-by: Tushar Nimkar <tnimkar@codeaurora.org>
Add change to immediately free the XO Clk GPIO after its usage.
Change-Id: Ie54e55175898e0c3e799ff8db8f3399011559f25
Signed-off-by: Umesh Vats <uvats@codeaurora.org>
Add debug registers to dump in the event of sync timeout for qsmmuv2.
Change-Id: I18cc3296e74ca0e2cb6f68f8aca67032d493410b
Signed-off-by: Prakash Gupta <guptap@codeaurora.org>
Disable VDD of MAX31760 and fan in RBC to save power.
Change-Id: I5156c17927af5d89adc67503ea7323f662b198c6
Signed-off-by: Minghao Zhang <minghao@codeaurora.org>
Ignore calibration request if its already in progress.
Change-Id: I8b516393fa1169263021403cc2e10160eac06615
Signed-off-by: Manikandan Mohan <manikand@codeaurora.org>
CNSS platform driver allocates host DDR memory for device.
This change exports these memory info to q5drv for QDSS streaming
feature.
Change-Id: I053704b0e146f50abd3940a91f2190ee1b2a7fe3
Signed-off-by: Kai Liu <kaliu@codeaurora.org>
Add feature support where a user can provide a custom list of TLMM
GPIOs associated with PDC pins for direct connect interrupt support.
This feature is needed because the TLMM GPIO PDC map is fixed per target
which is restrictive for a usecase where a custom list of direct connect
interrupts for GPIOs is needed.
Change-Id: Idc6e07a3405c7900445f25e60d08570f7b350fcc
Signed-off-by: Anant Goel <anantg@codeaurora.org>
To guarantee PCIe client MSI can wake up APPS while its in LPM,
call enable_irq_wake on the parent MSI, PCIe MSI IRQ. Doing so
will make sure these IRQs are not disabled as part of APPS system
suspend.
Change-Id: Ifdb74068a26eca7028667310d62df8b974e58927
Signed-off-by: Tony Truong <truong@codeaurora.org>
Few targets support 5 PCIe controller instances. Update logic
to support 5 PCIe RC controllers.
Change-Id: Iefe3c459e090226026ee03f5845f073cfe24e79f
Signed-off-by: Rama Krishna Phani A <rphani@codeaurora.org>
Do length check while mapping ion buffers to
avoid arbitrary physical memory read on DSP
which can lead to DOS.
Change-Id: I6334d4ceac795595aa3dc4bc71e6c736d2461c51
Acked-by: Deepika Singh <dsi@qti.qualcomm.com>
Signed-off-by: Jeya R <jeyr@codeaurora.org>
Enable SDC_QTI flag to add Qualcomm specific code to upstream
MMC driver.
Change-Id: I6121c683a00cdbce364e606a04d42e540ab8e894
Signed-off-by: Hiren Gohel <vhiren@codeaurora.org>
We would only enable/disable hw ice clk, we won't
set the frequency of this clk from ufs driver.
Change-Id: I25a482387facbf3fbbeb201d9513c4c042f10a0e
Signed-off-by: Nitin Rawat <nitirawa@codeaurora.org>
As per latest hardware programming guide, during
Hibern8 enter with power collapse:
SW should disable HW clock control for UFS ICE clock
(GCC_UFS_ICE_CORE_CBCR.HW_CTL=0), before ufs_ice_core_clk
is turned off (i.e GCC_UFS_*_ICE_CORE_CBCR[CLK_ENABLE]=0)
and vice versa during hibern8 exit.
This change updates UFS ICE clock disable sequence as per
recommended steps.
Change-Id: Ibe2036bb20a4e0ec368fc203da9553c10c02200d
Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org>
Signed-off-by: Ram Prakash Gupta <rampraka@codeaurora.org>
Update GPIO 127 for wake capability disablement on
Yupik.
Change-Id: I0edd431c2705b06cfaed1eea7b6769f3adeab315
Signed-off-by: Naman Padhiar <npadhiar@codeaurora.org>
Fix possible Buffer overflow due to double fetch from
fastrpc HLOS driver.
Change-Id: I03cf94e7f6fef9c8765404a6da3da47fe3bedf8b
Acked-by: Deepika Singh <dsi@qti.qualcomm.com>
Signed-off-by: Jeya R <jeyr@codeaurora.org>
Used under guest system, it submits GPU tasks into hardware while host
driver is unaware of it.
Hgsl communicates with GPU hardware using either GPU registers or
TCSR compute signaling hardware block.
Change-Id: I881941953ee2340a4c47f10e85e4b0a1dfb87a50
Signed-off-by: Kasin Li <donglil@codeaurora.org>
Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Thomas (Wonyoung) Yun <wyun@codeaurora.org>
On some targets, the slpi pin controller seems to be un-clocked
while trying to configure it. Enable clocked access while configuring
the slpi tlmm registers. Also, move the initialization from arch_initcall
to module_initcall due to the dependency with clock initialization.
Change-Id: I678fbb790b3200c28227c58ee3611b37d655bb9f
Signed-off-by: Yadu MG <ymg@codeaurora.org>
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
Add snapshot of virtual subsystem notification driver
from msm-4.14. This snapshot is taken as of msm-4.14
commit 035eb1f641f7 ("drivers: soc: qcom: Add snapshot of
virtual subsystem notification driver").
Change-Id: I8006342906e80e10ce2b2579f0dd0d89a072a6c5
Signed-off-by: Anant Goel <anantg@codeaurora.org>
This change disables the interrupt while requesting the IRQ else it
may cause interrupt imbalance. We are following similar way for all
the buses drivers.
Change-Id: I92c7ca2a3e6d58ef6aff5bbb577553b85596bb8c
Signed-off-by: Mukesh Kumar Savaliya <msavaliy@codeaurora.org>
