Commit graph

899,123 commits

Author SHA1 Message Date
Zhenhua Huang
df12e38f23 soc: qcom: mem-offline: online only valid memory blocks
mem-offline driver onlines blocks between memory_limit to end of DDR,
but for some cases when using large ram size, the range may not be
contiguous. We online un-existed memory blocks in this case. Example
-
RAM Entry 0 : Base 0x0080000000  Size 0x0033E00000
RAM Entry 1 : Base 0x0200000000  Size 0x0200000000
RAM Entry 2 : Base 0x0800000000  Size 0x0100000000
RAM Entry 3 : Base 0x00C0000000  Size 0x0140000000
if offline-size is 5GB and total memory size is 18GB, we onlined
also un-existed range [0x400000000,0x800000000] in
mem_online_remaining_blocks(). To fix this, Do parsing the DT tree
again and updated bitmap accordingly. Use this bitmap to online memory
blocks.

Change-Id: I5ea94a0ea9dca10e3a3311d6ea53a14302a41ae5
Signed-off-by: Zhenhua Huang <zhenhuah@codeaurora.org>
2021-06-04 01:30:31 -07:00
qctecmdr
e18073515c Merge "msm: kgsl: Update A635 GPU revision number" 2021-05-31 07:48:35 -07:00
qctecmdr
76c9e8d270 Merge "ARM: asm: Add etmv4x.h and debugv8.h to support etmv4 in arm32" 2021-05-31 07:48:34 -07:00
qctecmdr
0b0207bec8 Merge "mtd: msm_qpic_nand: Fix trival compilation errors" 2021-05-31 07:48:34 -07:00
qctecmdr
5143c1b90c Merge "leds: add initial driver for AW2016 LED device" 2021-05-31 07:48:34 -07:00
qctecmdr
96e2bf5666 Merge "icnss2: Avoid assert on QMI send failure" 2021-05-31 07:48:33 -07:00
qctecmdr
497d060f57 Merge "cpufreq: qcom: cpufreq-hw: Initialize sysfs attribute before usage" 2021-05-31 07:48:33 -07:00
qctecmdr
d0caa94887 Merge "arm: defconfig: Add video h/w accelerators support for MONACO" 2021-05-31 07:48:33 -07:00
qctecmdr
3c4e375b0a Merge "msm: kgsl: Enable ACD feature support for A635 GPU" 2021-05-31 07:48:32 -07:00
qctecmdr
4d5d6b55b8 Merge "clk: qcom: Update the clk structure parameters for GPUCC/DISPCC clks" 2021-05-31 07:48:32 -07:00
qctecmdr
5a1afe9087 Merge "arm64: defconfig: Enable v4 phy driver for blair" 2021-05-31 07:48:32 -07:00
Saurabh Sahu
1fdcce591e clk: qcom: Update the clk structure parameters for GPUCC/DISPCC clks
Update the halt check for gpu clocks and remove the enable_safe_config
for dispcc for MONACO.

Change-Id: I97f6a1b7b5d7f8aef862455f0bbf23f9b8612d79
Signed-off-by: Saurabh Sahu <sausah@codeaurora.org>
2021-05-31 16:33:03 +05:30
Hui Liu
817923dccf leds: add initial driver for AW2016 LED device
Add initial driver for AW2016 LED device
which can support up to 3 LED channels.

Signed-off-by: liweilei <liweilei@awinic.com>
Git-commit: ed6556f262cf7e2086d7728c2f752be4cf94b4d1
Git-repo: https://github.com/awinic-driver/aw2016.git
[huliu@codeaurora.org: move the driver to leds folder
 and make corresponding changes in Kconfig and Makefile,
 also remove the dtsi config file and modify the code
 style.]
Signed-off-by: Hui Liu <huliu@codeaurora.org>
Change-Id: I252ca2710d393ff6dcbb691a2a530433ffbd21e3
2021-05-31 14:09:26 +08:00
qctecmdr
9dd081c344 Merge "char: virtio_fastrpc: add interruptible invoke support" 2021-05-30 22:09:30 -07:00
Sachin Kumar Garg
8e0fd6fee5 arm: defconfig: Add video h/w accelerators support for MONACO
Moved the changes from monaco-debug.config to monaco.config

Change-Id: Ic9444738656249e75aff2de60865c170436b1fbc
Signed-off-by: Sachin Kumar Garg <sachinku@codeaurora.org>
2021-05-30 23:20:53 +05:30
Naman Padhiar
df36746b6c icnss2: Avoid assert on QMI send failure
There is possibility that ICNSS asserts on QMI send failure
even after receiving FW down indication. To avoid such scenario
check for FW down before ASSERT.

Change-Id: I68981879601e6fba459e9b48405eed370e00e6c6
Signed-off-by: Naman Padhiar <npadhiar@codeaurora.org>
2021-05-30 18:15:50 +05:30
Sharath Chandra Vurukala
dc9b3b95f1 net: config: remove USB_BAM unset from config
When enabling the VLAN configs USB_BAM config got
unset, correcting the change.

Change-Id: I40c3645b82051c890cacfc0144433d0e487ab6a3
Signed-off-by: Sharath Chandra Vurukala <sharathv@codeaurora.org>
2021-05-30 12:42:15 +05:30
qctecmdr
b8ce8e7c77 Merge "iio: qcom-spmi-adc5-gen3 : Update conversion and IRQ handling logic" 2021-05-29 20:04:04 -07:00
qctecmdr
37e7d96e56 Merge "defconfig: sdmsteppe: Enable CONFIG_QMP_DEBUGFS_CLIENT support" 2021-05-28 16:17:17 -07:00
qctecmdr
144af1f023 Merge "defconfig: gen3auto: Enable CONFIG_QMP_DEBUGFS_CLIENT support" 2021-05-28 16:17:16 -07:00
qctecmdr
54c6f0df18 Merge "arm64: defconfig: Enable MPM driver for SA2150P" 2021-05-28 16:17:16 -07:00
qctecmdr
4a81cc4587 Merge "drivers: rename-block: support DP and No DP configuration" 2021-05-28 16:17:14 -07:00
qctecmdr
ffc7cc1520 Merge "defconfig: Enable USB_BAM config for monaco" 2021-05-28 07:39:57 -07:00
qctecmdr
67951e4d8e Merge "qseecom: retry scm call if app is busy" 2021-05-28 07:39:57 -07:00
Jishnu Prakash
76e8f7ff93 iio: qcom-spmi-adc5-gen3 : Update conversion and IRQ handling logic
Fix timer value for immediate conversion to the right constant
to avoid TM conversions for immediate conversion requests.
Correct TM channel offsets checked from status and data registers
in TM interrupt handler.

Change-Id: I43a9a5cf33d31029fe306e61c4bf2e80966b9b7e
Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
2021-05-28 19:53:59 +05:30
Akshaya Bhat
797368e706 arm64: defconfig: Enable MPM driver for SA2150P
This change enables MPM interrupt controller driver for SA2150P.

Change-Id: I8ed7a03ac55abff2176b73e7fa4ac702aa8175ad
Signed-off-by: Akshaya Bhat <akshayab@codeaurora.org>
2021-05-28 19:35:33 +05:30
Venkata Rao Kakani
ede7e59086 drivers: rename-block: support DP and No DP configuration
Supporting renaming of partitions in DP and NON DP Configurations.

Change-Id: I1908d7e76157fa3e31378ea2981669379b2fca6b
Signed-off-by: Venkata Rao Kakani <vkakani@codeaurora.org>
2021-05-28 18:29:50 +05:30
Pradeep P V K
8fb75e15a8 mtd: msm_qpic_nand: Fix trival compilation errors
Fix the minor compilation errors: mixing declarations and
code [-Wdeclaration-after-statement] in nand driver.

Change-Id: I5dc76a47cc13b3246f9ecb8d24cf3a758a8b8bd1
Signed-off-by: Pradeep P V K <pragalla@codeaurora.org>
2021-05-28 17:59:01 +05:30
qctecmdr
a92cfc31ce Merge "soc: qcom: fix null pointer dereference issue" 2021-05-28 04:37:49 -07:00
qctecmdr
4b54ea1c9c Merge "icc: dt-bindings: add endpoint IDs for interconnects for QCS405" 2021-05-28 04:37:49 -07:00
qctecmdr
aa768f3d3d Merge "slatecom_interface: move header file to include path" 2021-05-28 04:37:48 -07:00
Vijayavardhan Vennapusa
02cc692b54 defconfig: Enable USB_BAM config for monaco
Enalbe USB_BAM config for monaco which is required for using
BAM2BAM path for QDSS over USB.

Change-Id: Iea75fea31f2a91f31168cbc134ec7f327b6e90e9
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
2021-05-28 16:12:56 +05:30
Nitin Rawat
bcf2a0d207 arm64: defconfig: Enable v4 phy driver for blair
This enables v4 phy driver for blair.

Change-Id: I63c50b41176618db8648841f95d25556cb91f648
Signed-off-by: Nitin Rawat <nitirawa@codeaurora.org>
2021-05-28 16:05:58 +05:30
qctecmdr
1dbbc6fc4f Merge "soc: qcom: pil: Proxy vote for QPIC clock during modem boot" 2021-05-28 01:26:25 -07:00
qctecmdr
e53f5d2456 Merge "drivers: soc: qcom: scmi_clients: add zero initialized entry in id table" 2021-05-28 01:26:24 -07:00
qctecmdr
dbff2620a9 Merge "iommu: iommu-debug: fix null-ptr-deref in atos write" 2021-05-28 01:26:23 -07:00
qctecmdr
ebca6aba88 Merge "msm: ADSPRPC: Re-use persistent map on static pd restart" 2021-05-28 01:26:23 -07:00
qctecmdr
70adcc2840 Merge "mac80211: fix possible oob and null pointer dereferenced issues" 2021-05-28 00:54:50 -07:00
qctecmdr
861472b711 Merge "slatecom-events-bridge: resolve errors" 2021-05-28 00:54:50 -07:00
qctecmdr
a32340e5d9 Merge "arm64: defconfig: Add mproc defconfig for sa5150p" 2021-05-28 00:54:49 -07:00
qctecmdr
ed74e035de Merge "cnss2: Increase delay between wlan_en & pcie reset" 2021-05-28 00:54:49 -07:00
Ping Jiang
3b01d63359 char: virtio_fastrpc: add interruptible invoke support
User invoke should be able to be interrupted by signal.
Use interruptible API in kernel to support such case.

Change-Id: I67bf35aa592ad80f69a07f5c4d077c103ccaebb3
Signed-off-by: Ping Jiang <scottjiang@codeaurora.org>
2021-05-28 15:40:30 +08:00
qctecmdr
41973f0671 Merge "rpmsg: glink: wait for intent request completion" 2021-05-27 07:23:20 -07:00
qctecmdr
26bd2a4e23 Merge "cnss2: Add link status check before dumping MHI registers" 2021-05-27 07:23:20 -07:00
qctecmdr
552ef3bee0 Merge "arm64: defconfig: Enable PCIe controller for direwolf" 2021-05-27 07:23:19 -07:00
qctecmdr
b5297abc95 Merge "msm: pcie: add support for cnoc_qx, pipediv2_clk" 2021-05-27 07:23:19 -07:00
qctecmdr
895c47cd7f Merge "defconfig: Enable CONFIG_REGULATOR_QTI_DEBUG" 2021-05-27 07:23:19 -07:00
qctecmdr
9fd9a0c73e Merge "soc: qcom: pmic_glink: Use SERVREG_NOTIF_SERVICE_STATE_DOWN_V01 for PDR" 2021-05-27 07:23:18 -07:00
Arun Prakash
e8cd7f5045 arm64: defconfig: Add mproc defconfig for sa5150p
Add mproc related defconfig for sa8155 which inlcudes
qrtr,hwspinlock,mailbox,glink,smem,smp2p and ipc logging
related configurations.

Change-Id: I1ae37f28648c78fdf14fe2f6ba1cdcbb453f464b
Signed-off-by: Arun Prakash <app@codeaurora.org>
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
2021-05-27 19:42:03 +05:30
Pankaj Gupta
871cd6e975 msm: kgsl: Update A635 GPU revision number
A635 GPU correct revision number is A642L. Update the
revision and revision checks to reflect correct value.

Change-Id: I92a856cdf8775354216ffa64f6f1fdd86346daf2
Signed-off-by: Pankaj Gupta <gpankaj@codeaurora.org>
2021-05-27 05:11:16 -07:00