Commit graph

886,765 commits

Author SHA1 Message Date
qctecmdr
e3d2fc1968 Merge "leds: qti-flash: Support zero duration for flash safety timer" 2020-07-20 23:34:41 -07:00
qctecmdr
74c727c1ed Merge "soc: qcom: spcom: spcom vote for PM runtime suspend/resume" 2020-07-20 23:34:40 -07:00
qctecmdr
5f88a4269c Merge "Revert "scsi: ufs: Dump PA_VS_STATUS_REG1 in eh"" 2020-07-20 23:34:40 -07:00
qctecmdr
5094ac8619 Merge "mhi: core: Use appropriate names for BHI/BHIe firmware load functions" 2020-07-20 23:34:39 -07:00
qctecmdr
f93f89138c Merge "kernel: add header file for audio compressed formats in bp" 2020-07-20 23:34:37 -07:00
qctecmdr
850ca920cb Merge "arm: dma-mapping: Use iommu_dma ops for arm32" 2020-07-20 23:34:36 -07:00
qctecmdr
43aa526391 Merge "platform: msm-geni-se: Return correct Error code in probe context" 2020-07-20 21:09:20 -07:00
qctecmdr
57c815c3b2 Merge "serail: msm_geni_serial: Stop TX Engine during port close" 2020-07-20 21:09:20 -07:00
qctecmdr
a4a2f10e67 Merge "irqchip: qcom-pdc: Add support to load PDC on shima as module" 2020-07-20 21:09:19 -07:00
qctecmdr
418f6226db Merge "arm64: defconfig: Disable CONFIG_CFI_PERMISSIVE flag" 2020-07-20 21:09:19 -07:00
qctecmdr
1ff72e6864 Merge "firmware: scm: Remove arch check for dma_set_mask" 2020-07-20 12:16:06 -07:00
qctecmdr
a7d4628040 Merge "soc: qcom: rpmh-rsc: Set suppress_bind_attrs flag" 2020-07-20 12:16:05 -07:00
qctecmdr
dde87f7fae Merge "interconnect: qcom: Add SDC1 master for Shima" 2020-07-20 12:16:05 -07:00
qctecmdr
85f242f759 Merge "arm64: defconfig: Add support for DISPCC, debugCC for SHIMA" 2020-07-20 08:45:51 -07:00
qctecmdr
67cb4fbaf4 Merge "clk: qcom: Add support for pm ops for Multimedia clock controllers" 2020-07-20 08:45:50 -07:00
qctecmdr
ec92655704 Merge "scsi: ufs: Clear uic_cmd->cmd_active before calling complete()" 2020-07-20 08:45:50 -07:00
qctecmdr
a539b642f4 Merge "qseecom: Change in buffer sharing mechanism in qseecom" 2020-07-20 08:45:50 -07:00
qctecmdr
b2198c494f Merge "drivers: qcom: stats: define readq_relaxed for ARM variants" 2020-07-20 08:45:49 -07:00
qctecmdr
b83f0c9796 Merge "clk: qcom: debugcc: Add debug clock controller support for SHIMA" 2020-07-20 03:11:40 -07:00
qctecmdr
a6ceb8782b Merge "clk: qcom: Update GCC/GPUCC code for HOLI" 2020-07-20 03:11:39 -07:00
qctecmdr
7aa09639a4 Merge "defconfig: lahaina: Fix INTERCONNECT_TEST being disabled for QGKI" 2020-07-20 03:11:39 -07:00
qctecmdr
97f35d5f2d Merge "pinctrl: qcom: Update pinctrl for HOLI soc" 2020-07-20 03:11:39 -07:00
qctecmdr
0e975c6686 Merge "input: touchscreen: synaptics_tcm: add new touch driver" 2020-07-20 00:21:23 -07:00
qctecmdr
97913a8a95 Merge "icc: dt-bindings: Update endpoint IDs for interconnects for HOLI" 2020-07-20 00:21:23 -07:00
Yogesh Lal
c452695ca7 arm64: defconfig: Disable CONFIG_CFI_PERMISSIVE flag
Holi build looking for __cfi_sowpath_diag which is no
longer exported by the kernel. So, build was failing with
undefined symbol error. To fix it disabling CONFIG_CFI_PERMISSIVE.

Change-Id: I6381c28ae3d476a03a56b7b1e35a257a060e8cb2
Signed-off-by: Yogesh Lal <ylal@codeaurora.org>
2020-07-20 10:11:22 +05:30
qctecmdr
7cb2052d4a Merge "ufs: ufs-qcom: Fix racing caused by ufs_qcom_testbus_config()" 2020-07-19 21:01:11 -07:00
qctecmdr
08dcb823ac Merge "sound: usb: qmi: Move QMI service init to driver probe" 2020-07-19 21:01:11 -07:00
qctecmdr
54a634f9d4 Merge "ABI: Update internal whitelist with hyp assign" 2020-07-19 21:01:11 -07:00
qctecmdr
90bec1c521 Merge "coresight-tmc: Use sysfs_buf for byte-cntr and sw usb cases" 2020-07-19 21:01:10 -07:00
qctecmdr
c5289e457d Merge "dt-bindings: clock: Update clock ID's of GPUCC and DISPCC for SHIMA" 2020-07-19 21:01:10 -07:00
Odelu Kukatla
649dce9082 interconnect: qcom: Add SDC1 master for Shima
Add SDC1 master port as it is for client to request
the bandwidth.

Change-Id: Ib459a6f156df05f088c0ec5a58b6dbb73cb39a5f
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
2020-07-18 09:19:36 -07:00
Odelu Kukatla
439afcdc16 icc: dt-bindings: Add SDC1 master ID for Shima
Add SDC1 master ID as it is for client to request
the bandwidth.

Change-Id: I2be2c4866a64a1a2ade2299d7d9b78f4e2d85933
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
2020-07-18 21:18:12 +05:30
Jagadeesh Kona
27c20c3a1c arm64: defconfig: Add support for DISPCC, debugCC for SHIMA
Enable Display and debug clock controllers for SHIMA.

Change-Id: I69b8e770c8f286d32f6ebfd876284bf52a74c380
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
2020-07-18 06:00:08 -07:00
Jagadeesh Kona
577b5c7e15 clk: qcom: debugcc: Add debug clock controller support for SHIMA
Add debug clock controller to support measure functionality for all
clock controllers.

Change-Id: I4fde3ad197220264329126ca788aa70a7c75bcb7
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
2020-07-18 06:00:00 -07:00
Jagadeesh Kona
dcc0bc3e74 clk: qcom: dispcc: Add display clock controller for SHIMA
Add the display clock controller to support display port
related branches, PLLs and RCGs.

Change-Id: I3f366c3880823199ed4cd34bb9e608baf804e1bc
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
2020-07-18 18:29:09 +05:30
Mao Jinlong
1ebe55d92e coresight-tmc: Use sysfs_buf for byte-cntr and sw usb cases
Etr_buf will be NULL when disable etr hw. It is before stopping byte-cntr
and sw usb data transfer which may cause null pointer issue. Use sysfs_buf
to avoid this issue.

Change-Id: I5967fd4183a9f36fca22059bb08fd8d357c8e5af
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
2020-07-18 14:11:35 +08:00
Jagadeesh Kona
97f4757fee clk: qcom: Add support for pm ops for Multimedia clock controllers
Add support for pm ops for Camera, Graphics and Video clock
controllers.

Change-Id: Ic9c01a35385a8c24899b66c9652810135bc42ac7
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
2020-07-17 20:27:12 -07:00
Jagadeesh Kona
83b7c09872 ABI: Add pm_clk* symbols to qcom whitelist
Add pm_clk_add, pm_clk_create, pm_clk_destroy, pm_clk_resume,
pm_clk_suspend symbols to qcom whitelist.

Change-Id: I166bdc86bba786161d2148b7a63d2f6f75777694
Signed-off-by: Jagadeesh Kona <jkona@codeaurora.org>
2020-07-18 08:54:18 +05:30
Guru Das Srinagesh
ab808011ad leds: qti-flash: Support zero duration for flash safety timer
The minimum timeout that can be set is 10 ms due to the clamping being
done in led_set_flash_timeout() in the flash LED class framework. Change
the minimum to allow zero timeout to be set, and also disallow setting
strobe in this case.

Change-Id: Ic34057197c05daf640c2a7d21cbae8e4638319ee
Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org>
2020-07-17 17:48:42 -07:00
Guru Das Srinagesh
1a00e83287 leds: qti-flash: Fix debug prints, read more than one byte
Print the data instead of the pointer in qti_flash_led_write(), update
the print in qti_flash_led_masked_write(), and fix qti_flash_led_read()
so that it returns a pointer to more than one byte.

Change-Id: Ic9cbc35a6552f8978ff9e36da2aafeec69885b9a
Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org>
2020-07-17 17:48:42 -07:00
Jack Pham
8f354a41fe sound: usb: qmi: Move QMI service init to driver probe
When registering the QMI server during initialization there is
a chance that the handle creation can fail with -EPROBE_DEFER if
the IPC router service isn't ready yet. In that case, we should
not fail the module_init call as that results in the module
getting unloaded with no automatic mechanism to reload it (a la
driver probe deferral). Instead, move the uaudio_qmi_svc_init()
call to beginning of uaudio_qmi_plat_probe() so that in case it
defers the probe can be retried again later.

Change-Id: I07a1e2cee5194387884cb716e95ed7c414a22159
Signed-off-by: Jack Pham <jackp@codeaurora.org>
2020-07-17 12:09:08 -07:00
Mukesh Ojha
f9fde8988f interconnect: qcom: Compile Shima interconnect provider driver
Add the shima driver file compilation on INTERCONNECT_QCOM_SHIMA
config.

Change-Id: I2148f176f6c2a8b2232df790391e54a819302b48
Signed-off-by: Mukesh Ojha <mojha@codeaurora.org>
2020-07-17 11:07:56 -07:00
Kunlei Zhang
5a61ae90da ABI: Update internal whitelist with hyp assign
Update internal whitelist with hyp assign.

Change-Id: I89bf58600a53ea8cdb8b6aa4c5f87ed4b35421b9
Signed-off-by: Kunlei Zhang <kunleiz@codeaurora.org>
2020-07-17 23:17:35 +08:00
Anmolpreet Kaur
7b0010980f qseecom: Change in buffer sharing mechanism in qseecom
Copy the entire userspace request buffer to local kernel
buffer and use that to send to TZ. Update the response
received in the local buffer to the actual userspace buffer
after the request is complete.

Change-Id: I673d74a32966816c5248778fc967eb91da5b6df5
Signed-off-by: Anmolpreet Kaur <anmolpre@codeaurora.org>
2020-07-17 05:36:13 -07:00
Lina Iyer
eb798d82d2 firmware: scm: Remove arch check for dma_set_mask
Remove the preprocessor if statement for checking the arch of the
target since this will not affect targets with a 32bit address space. This
change allows the driver to be compiled and used for targets that do not
define CONFIG_ARM64.

Change-Id: I6fc11e86d6799099fdaeec46df6d7093c1ca117f
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Tushar Nimkar <tnimkar@codeaurora.org>
Signed-off-by: Siddharth Gupta <sidgup@codeaurora.org>
2020-07-17 17:34:33 +05:30
Lina Iyer
963b168fc2 cpuidle: lpm-levels: no hotplug for single core
Register for hotplug and dev_pm_qos notification only
for SMP so covering under CONFIG_SMP flag.

Change-Id: Ic3da9648a4dd5c762cd97dbb9f1915f79bd2481e
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Tushar Nimkar <tnimkar@codeaurora.org>
2020-07-17 17:33:27 +05:30
Lina Iyer
6757e16bd0 drivers: qcom: rpmh: allow RPMH on ARM SoC
Remove config restriction for RPMH on ARM64 platforms
only.

Change-Id: Id783ad288098e09294eefbff2982af5670c3ab54
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Tushar Nimkar <tnimkar@codeaurora.org>
2020-07-17 17:31:41 +05:30
Lina Iyer
e5fb789453 drivers: irqchip: pdc: Add irqchip for sdxlemur
Declare PDC irqchip support for sdxlemur.

Change-Id: I2ac3f67b71cc092024ea8a3d13e31571cd2bc898
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Tushar Nimkar <tnimkar@codeaurora.org>
2020-07-17 17:30:08 +05:30
Lina Iyer
8d6b711a9f drivers: qcom: stats: define readq_relaxed for ARM variants
ARM cannot natively read 64-bit address. As such the readq_ variants
are not defined for this architecture. Add a 32-bit equivalent to read 2
sequential 4-byte memory into a u64 value. Let's keep them locally
defined for now, since they are not native to the ARM architecture.

Change-Id: Ib0ce08c3b8a37af85c12c2ad72803bf871847f67
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Tushar Nimkar <tnimkar@codeaurora.org>
2020-07-17 17:27:27 +05:30
Saurabh Sahu
ab5f1435fc clk: qcom: Update GCC/GPUCC code for HOLI
Update the gpll configuration values for GCC and GPUCC
and halt check for camera and video ahb clks for GCC
in HOLI.

Change-Id: I637b05f0ecc877a2d83990532b34462de28069de
Signed-off-by: Saurabh Sahu <sausah@codeaurora.org>
2020-07-17 16:57:00 +05:30