This is a snapshot of MSM PCIe root complex as of msm-4.19
commit 6e2242593d4a ("drm/msm/dp: check for invalid seqno before
clearing a txmsg slot").
Changes made:
- remove or switch to sysfs for all module params
- move from MSM bus to ICC framework
- replace all snprintf with scnprintf
- update debugfs remove
- update license for msm_pcie.h
- misc syntax improvements
Change-Id: I310fdfd136346f74c20806bd5dcdbc74c7d894a3
Signed-off-by: Tony Truong <truong@codeaurora.org>
Enable compilation of fastrpc driver as DLKM module on Lahaina.
This driver will be part of Lahaina GKI config.
Change-Id: Ie34249640949b192557735ccc64ffd75526b48ed
Signed-off-by: Edgar Flores <edgarf@codeaurora.org>
Generate a new irqchip struct for each pinctrl device that is
registered to avoid sharing the same irqchip between devices.
This corrects the following error which is printed when
registering more than one pinctrl-spmi-gpio device:
"detected irqchip that is shared with multiple gpiochips:
please fix the driver."
Change-Id: I80ce67fc674b96f4386499f547395ceed7480583
Signed-off-by: David Collins <collinsd@codeaurora.org>
Add support for qcom,pmr735a-gpio and qcom,pmr735b-gpio variants.
Change-Id: I773d2539af146be56b091ced8709ae8dabe6e36e
Signed-off-by: David Collins <collinsd@codeaurora.org>
Now with GKI, SMMU CB can be delayed in probe
due to dependencies. The change waits for the
probe before triggering fw loading and post_init
call.
Change-Id: I468edd730a91de01ba9619385ab0c76083bc9382
Signed-off-by: Ghanim Fodi <gfodi@codeaurora.org>
The VADC architecture on PMIC7 is changed as compared to PMIC5. The
major change from PMIC5 is that all SW communication to ADC goes through
PMK8350, which communicates with other PMICs through PBS when the VADC
on PMK8350 works in master mode. The SID register is used to identify the
PMICs with which the PBS needs to communicate. Add support for the same.
Change-Id: If5c651e01be9363a61d1bf546e0b6d82a023904c
Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
Add definitions for ADC channels and scaling function IDs for PMIC7
ADC drivers. Add virtual channel definitions per PMIC, to be used
by ADC clients for PMIC7.
Change-Id: If857612a8087b928901dc08327aea3a8f4df7b01
Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
To update QMAP ID there is no need to start and stop the GSI
channel. Make changes to read only scratch2 register for WDI3
protocol and update the QMAP ID without affecting other registers.
Change-Id: I7f873386fd01d624629fed15b841c6abd558a9ce
Signed-off-by: Chaitanya Pratapa <cpratapa@codeaurora.org>
If back to back SSR is triggered there is a possibility
of race condition where we try to send QMI sync indication
with a invalid handle. Make a change to validate the handle
before sending the indication.
Change-Id: If912b6676b562bd4a23c68512e9c80e6c0ac7a49
Signed-off-by: Chaitanya Pratapa <cpratapa@codeaurora.org>
Partial packets are not expected to be receievd on WAN_CONS
pipe. Make changes to handle gracefully if EOB packets
are received on WAN_CONS pipe in cases where network is
misbehaving.
Change-Id: I4a4ce96a0c86f353e1764d016edbb00011367205
Signed-off-by: Chaitanya Pratapa <cpratapa@codeaurora.org>
When MHI pipes are disconnected, host doesn't expect any
further communication from device. Make a change to not
to update the state during pipe disconnect.
Change-Id: Ia2315e3a94049ba3adda4b42d363ce2f7108d89f
Signed-off-by: Chaitanya Pratapa <cpratapa@codeaurora.org>
This change enables spcom driver on Lahaina.
Change-Id: Ia8cbb369c3dd201389f83c8183dc573ecec71bb2
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
There could be cpufreq hw where accumulative cycle counters are not
supported. Add a device tree property to identify the same.
On those hardware the cycle counter needs to be read from core-0 of the
frequency domain.
Change-Id: Ib7969b2c5aaaf78f7c8359d7c417b9453e6c1f2f
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Initialization of the spinlock is required to avoid the below trace.
cpufreq: driver qcom-cpufreq-hw up and running
BUG: spinlock bad magic on CPU#7, swapper/0/1
lock: qcom_cpufreq_counter+0x128/0x140, .magic: 00000000,
.owner: <none>/-1, .owner_cpu: 0.
Change-Id: I079ebd7c0009c3b634d2d5d41ac880da06cf8f6d
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Update the cpufreq hardware register offsets data for non EPSS devices to
be able to parse the LUTs of frequency and voltage.
Re-introduce the commit '00319840a4af ("cpufreq: qcom-hw: Update freq_scale
from fast_switch path")'
The freq_scale maintained by the topology driver needs to be updated when
the frequency is transitioned. Without this, the current capacity of a CPU
metric gets broken in the scheduler.
The current code calls arch_set_freq_scale() from the target_index method
but not from the fast_switch method. Fix this.
Change-Id: I2789b76f14b4c0fe8ad52b449ed9f4ea3a4bff32
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The freq_scale maintained by the topology driver needs to be
updated when the frequency is transitioned. Without this,
the current capacity of a CPU metric gets broken in the scheduler.
The current code calls arch_set_freq_scale() from the target_index
method but not from the fast_switch method. Fix this.
Change-Id: I92cafba9ffd4a70c8a06ed54e4e410336de4d453
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This is in preparation for updating the current driver to the upstreamed
code. Add support to take care of EPSS firmware related code.
Change-Id: I4bd4165a8457dcaedc26d3bc8704db0c886832ed
Signed-off-by: Taniya Das <tdas@codeaurora.org>
