The display connector_init fails if the thermal cooling device
property "#cooling-cells" is not present under the mdss_mdp DT node.
Earlier this property used to be defined in "<target>-thermal-overlay.dtsi"
file, because of this, sometimes it gets missed.
Looking at the code of the sde_connector, it appears the "#cooling-cells"
is a mandatory property of the mdss_mdp.
Add this property under mdss_mdp DT node.
Change-Id: Icd4b076e0c718327df762f0dae10347162fa2299
This change reverts commit 8198c2b43d6e ("reduce transfer
time by 100 usec in yupik target"). The oriGinal issue of
unstable fps on cphy panels will be fixed with commit
72f31fb34b ("disp: msm: dsi: update CPHY command mode
clock calculation").
Change-Id: I57ab55416c1fd264b49f9097738942c2b9471096
Currently the dsi clock handles are under the dsi controller DT
node. As soon as the controller probe finishes, the dispcc sync
state can get called before the dsi_display probe potentially
disturbing the clock votes. dsi_display adds its component to the
list of components hence controlling the bind which adds the dsi
clock votes. There is no separate component for the dsi_ctrl.
Hence we are no longer protected by the component model in this
case against the disp cc sync state getting triggered after the
dsi_ctrl probe. To protect against this incorrect sync state trigger
add a dummy MDP clk vote handle to the dsi_display DT node. Since
the dsi_display driver does not parse MDP clock nodes, no actual
vote shall be added and this change is done just to satisfy sync
state requirements.
Change-Id: I4c4baf15171a13a066a3383bdc1242279809444d
Currently the dsi clock handles are under the dsi
controller DT node. As soon as the controller probe
finishes, the dispcc sync state can get called before
the dsi_display probe potentially disturbing the clock
votes for cont_splash use case. dsi_display adds its
component to the list of components hence controlling the
bind which adds the dsi clock votes. There is no separate
component for the dsi_ctrl. Hence we are no longer
protected by the component model in this case against the
disp cc sync state getting triggered after the dsi_ctrl
probe. To protect against this incorrect sync state trigger
add a dummy MDP clk vote handle to the dsi_display
DT node. Since the dsi_display driver does not parse
MDP clock nodes, no actual vote shall be added and this
change is done just to satisfy sync state requirements.
Change-Id: I47c458f4f6f2937effdd1212496b41eacab4e052
Add 120Hz nt36672e Video mode panel support on yupik
idp platform. Also, enable DFPS and ESD feature for
the panel.
Change-Id: Ic8e0bf998c3ebf83fba917389754326b39bbac96
Add 144hz video, 120hz cmd, and video modes for qrd device.
And also enable 120hz cmd dynamic fps switch, 144hz, and 120hz
video dfps feature.
Change-Id: I5a2e896cf0ad9c3ce8bfd8f4de421385ae98c15e
Add r66451 60hz cphy command mode panel for qrd yupik, and enable RFI
and ESD check for this panel.
Change-Id: Ibfbb942c4a2747db9b80b0c81cf9cef40803517b
