There can exist a race where we clear the A6XX_RBBM_INT_0_MASK
register while the gpu is going into IFPC. Fix this by clearing this
register before clearing the OOB.
Change-Id: I08e9dbccbfdbee93ba7ef35fbbc673938ee033da
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
This ensures that dcvs runs while the gpu is still actively working
on the same submission for longer than the idle timer.
Change-Id: I85f2ff21dc19a9e589d6ed918bebea4c42b2a39d
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
This property is used to enable dcvs or disable both dcvs and slumber
using kgsl power state transitions. Since gmu or rgmu based targets
don't use the power states, add and use gmu core flag to enable and disable
slumber for those targets.
Change-Id: Iace3af9427c7b84509c9041604972cf14e7cd675
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
Disable gpu interrupt inline instead of changing power states as gmu
based targets do not implement the power state machine. Make sure we
skip turning off the gpu interrupt during reset after stall on fault.
Change-Id: I49c1702005f88eab523f00b25923c9c65193c7ca
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
There was a missing EXPORT_SYMBOL() for some public APIs. Add
those statements to ensure clean builds so KOs can use them.
Change-Id: Iaac851ddad0b729208804320f02133d0fa039615
Signed-off-by: Bhaumik Bhatt <bbhatt@codeaurora.org>
2G+5G+6G, total channel num is 157 until now, increase unsafe channel max
num to avoid out of buffer.
Change-Id: I1e433c0bd88290bb5493b2c4b0bda86e17b04a01
CRs-Fixed: 2752689
Signed-off-by: Jianmin Zhu <jianminz@codeaurora.org>
Signed-off-by: Manikandan Mohan <manikand@codeaurora.org>
Fixes in qseecom driver to support shmbridge and
change parameters as hypervisor expects them to
be.
Change-Id: I57dc5d6fe7b74b45da2dee6de32c1251d77275ee
Signed-off-by: Anmolpreet Kaur <anmolpre@codeaurora.org>
Send SMMU IOVA range to Firmware only when SMMU S1 stage is
enabled.
Change-Id: I3d0d0b6ad3db18aded0d921f79337cf845ceb5f4
Signed-off-by: Naman Padhiar <npadhiar@codeaurora.org>
