qctecmdr
3bf0b189b3
Merge "ARM: dts: msm: Update modem Tj configuration for Lahaina"
2020-07-10 03:37:13 -07:00
qctecmdr
3acc4d7140
Merge "bindings: clock: Add debugcc bindings for HOLI"
2020-07-10 03:37:13 -07:00
qctecmdr
ff733d40ae
Merge "ARM: dts: msm: Update audio codec device tree configuration"
2020-07-09 06:59:31 -07:00
qctecmdr
020e8f7cc1
Merge "ARM: dts: msm: Add audio hw vote clock node in lpi"
2020-07-09 06:59:31 -07:00
qctecmdr
1de8319607
Merge "ARM: dts: msm: Add NSP junction mitigation rule for Lahaina"
2020-07-09 06:59:30 -07:00
qctecmdr
edbfa839e6
Merge "dt-bindings: ufs: Add compatible string for holi phy driver"
2020-07-09 06:59:30 -07:00
Taniya Das
1a2f44b06d
bindings: clock: Add debugcc bindings for HOLI
...
Debug Clock controller required for clock measure functionality.
Change-Id: I6c34299b381040fd72f44f86d8210f8078de7b00
2020-07-08 12:28:41 +05:30
Meng Wang
5137bab5ad
ARM: dts: msm: Add audio hw vote clock node in lpi
...
Add audio hw vote clock node in lpi device tree
in order to support digital clk resource manager
in lahaina targets.
Change-Id: Id64fdd5f07a8408ddb6ebb6247c3c741f22d2785
2020-07-07 14:14:52 +08:00
qctecmdr
05f34477ea
Merge "ARM: dts: msm: Update Graphics clock controller node for HOLI"
2020-07-05 05:41:10 -07:00
Taniya Das
484a609b23
ARM: dts: msm: Update Graphics clock controller node for HOLI
...
Update to define the regulator/clocks phandle for GPUCC and also update
the GDSC to use the regulator gdsc driver.
Change-Id: I8171169c29adeb3a774509ed3a651495ca477c12
2020-07-05 03:22:12 -07:00
qctecmdr
329c91a8ae
Merge "dt-bindings: kgsl: Add device tree bindings for GPU core properties"
2020-07-05 01:35:12 -07:00
Deepak Kumar
3273ba362a
dt-bindings: kgsl: Add device tree bindings for GPU core properties
...
Add "qcom,adreno-gpu-a660-shima" compatible string bindings for GPU
core properties. New compatible string is to enable GPU feature set
specific to Shima SOC.
Change-Id: I1a4e5d17b4700846b6adcec41595f14061347074
2020-07-05 12:39:42 +05:30
qctecmdr
2f8ee6d0a1
Merge "ARM: dts: msm: Update secure display heap id with macro"
2020-07-04 22:53:51 -07:00
qctecmdr
83790f57f4
Merge "ARM: dts: msm: Update secure display heap id with macro"
2020-07-04 22:53:51 -07:00
qctecmdr
856f7888a6
Merge "dt-bindings: Add documentation for UFS's vcc-voltage-level"
2020-07-04 22:53:51 -07:00
qctecmdr
9212782818
Merge "ARM: dts: msm: Add node for max tdm slots for lahaina"
2020-07-04 22:53:51 -07:00
qctecmdr
902cb3c038
Merge "ARM: dts: msm: Adding fastrpc and cdsp device nodes"
2020-07-04 22:53:51 -07:00
qctecmdr
a5dab5e38c
Merge "ARM: dts: msm: Update USB HSPHY related override parameters on Lahaina"
2020-07-04 22:53:51 -07:00
qctecmdr
1f63a0afcc
Merge "ARM: dts: msm: Add support for CPUFREQ HW for HOLI"
2020-07-04 14:21:04 -07:00
qctecmdr
cf7a69b1fa
Merge "ARM: dts: msm: Update audio routing for voice activation usecase"
2020-07-04 10:39:43 -07:00
qctecmdr
cf61e1e193
Merge "ARM: dts: msm: Open NOM_L1 gpu powerlevel for A660 v1"
2020-07-04 10:39:43 -07:00
qctecmdr
03f9bcd664
Merge "ARM: dts: msm: Add flags to estimate thresholds for BCL in lahaina"
2020-07-04 10:39:42 -07:00
Nitin Rawat
8eacfdd145
dt-bindings: ufs: Add compatible string for holi phy driver
...
This change add compatible string information for holi
phy driver.
Change-Id: I0efb673a551c7fdf57b454906ae9010da3d1380f
2020-07-04 21:14:05 +05:30
qctecmdr
c2ef6bea52
Merge "ARM: dts: msm: Add stub interconnect devices for sdxlemur"
2020-07-04 04:29:30 -07:00
qctecmdr
c0fbc6296f
Merge "ARM: dts: msm: Update RPM-SMD clock node for HOLI"
2020-07-03 22:59:54 -07:00
qctecmdr
1f59c06aec
Merge "dt-bindings: Add documentation wlan platform driver"
2020-07-03 22:59:54 -07:00
qctecmdr
e0350cc1a8
Merge "ARM: dts: msm: Add rmtfs_sharedmem support for Shima"
2020-07-03 22:59:54 -07:00
qctecmdr
64bea02e81
Merge "ARM: dts: msm: Add memshare for lahaina"
2020-07-03 17:48:40 -07:00
qctecmdr
3509258440
Merge "ARM: dts: msm: Disable L1SS sleep for Lahaina"
2020-07-03 17:48:40 -07:00
qctecmdr
e49daff97c
Merge "ARM: dts: msm: Include sdxlemur stub regulator"
2020-07-03 12:28:53 -07:00
qctecmdr
a6f8feba47
Merge "ARM: dts: msm: Add coreisght device tree for shima"
2020-07-03 12:28:53 -07:00
qctecmdr
a7580172cb
Merge "ARM: dts: msm: Add LPASS pil node for Holi SoC"
2020-07-03 12:28:53 -07:00
Sandeep Singh
88777d15ec
dt-bindings: Add documentation wlan platform driver
...
This change add entry of wlan platform driver for iWCN
architecture.
Change-Id: Ic89fb32a944eaefe88a568e6b998b475c7dd68ea
2020-07-03 06:28:21 -07:00
qctecmdr
aed7ab7fd4
Merge "ARM: dts: msm: Add IPCC register range"
2020-07-03 04:10:15 -07:00
qctecmdr
7372aad95a
Merge "ARM: dts: msm: Enable symmetry in Lahaina led switch devices"
2020-07-03 04:10:15 -07:00
qctecmdr
c86cb7aabd
Merge "ARM: dts: msm: Update clock nodes and GDSC for SHIMA"
2020-07-03 04:10:15 -07:00
qctecmdr
7d3e5e7b8b
Merge "dt-bindings: mailbox: Add compatible for sdxlemur"
2020-07-03 04:10:15 -07:00
qctecmdr
07856c8719
Merge "ARM: dts: msm: Add VADC and ADC_TM nodes for holi"
2020-07-02 22:46:55 -07:00
Ram Chandrasekar
21a6862a86
ARM: dts: msm: Update modem Tj configuration for Lahaina
...
Update modem Tj configuration to do incremental mitigation starting 95C
to 105C, with 5C hysteresis.
Change-Id: I3ed97d024e8e4ff47c0e47d041959e98e4a6b2d3
2020-07-02 13:04:58 -07:00
Mohammed Mirza Mandayappurath Manzoor
026aa276ab
ARM: dts: msm: Open NOM_L1 gpu powerlevel for A660 v1
...
Expose NOM_L1 power level for A660 v1 devices.
Change-Id: I3ca084c3c6fb24a9ffc26c33505d01c6f40b52a8
2020-07-02 10:28:38 -07:00
Sudheer Papothi
c46bbcbf15
ARM: dts: msm: Update audio codec device tree configuration
...
Update audio codec device tree configuration on lahaina to
ensure the modules will be called in sequence.
Change-Id: Id3aae3f31d9b31b5f85545d5db61212ff548c7db
2020-07-02 08:46:29 +05:30
Hemant Kumar
bdcff7e7b9
ARM: dts: msm: Disable L1SS sleep for Lahaina
...
Remove the software workaround to manually manage
the phy PLL. Keep the phy PLL on all the time by
disabling L1SS sleep. This is required to prevent
PCIe link down issue upon exiting the L1SS sleep.
Change-Id: I6251f05d1ae0572b958740460606e3eeb51c59ed
2020-07-01 11:51:58 -07:00
Rajeshwar Kurapaty
f5ab02ac80
ARM: dts: msm: Update secure display heap id with macro
...
Update secure display heap id with ION_SECURE_DISPLAY_HEAP_ID
Change-Id: I527f2ac2fd6dee486dd2fde2b4542ce3f720de9b
2020-07-01 09:17:55 +05:30
Rajeshwar Kurapaty
8e43dc055d
ARM: dts: msm: Update secure display heap id with macro
...
Update secure display heap id with ION_SECURE_DISPLAY_HEAP_ID
Change-Id: I00a9a04b65aab7bf25b7ab3ef1ed6ff2758d159f
2020-07-01 09:01:58 +05:30
Bao D. Nguyen
7d510d2961
dt-bindings: Add documentation for UFS's vcc-voltage-level
...
Add documentation for the UFS's vcc-voltage-level.
Change-Id: I8bb21513f1244f841b871d8eb25ec95259f66932
2020-06-30 16:05:31 -07:00
Yogesh Lal
d1a9f63c8d
ARM: dts: msm: Add LPASS pil node for Holi SoC
...
Add LPASS pil node for LPASS subsystem loading for Holi.
Change-Id: I254b2aa071afc74828152be2bec0dd8c7f50fb73
2020-06-30 09:21:06 +05:30
Yogesh Lal
861f194e1f
ARM: dts: msm: Add scm node for Holi SoC
...
Enable scm node to support subsystem pil loading for Holi.
Change-Id: I750b1d87310088486fd005ad9ce4943fa3e94c4b
2020-06-30 09:20:40 +05:30
Ram Chandrasekar
9f8afd4aa7
ARM: dts: msm: Add flags to estimate thresholds for BCL in lahaina
...
Mention the new property qcom,pmic7-threshold for the BCL device in
lahaina, so that the software will account for the no bit shift in the
threshold register.
Change-Id: Id939e2eaa64235645cd2948dfba0fbcd3ab6bd8b
2020-06-29 11:25:32 -07:00
Ram Chandrasekar
ba262f666c
dt-bindings: thermal: Add a property to account BCL threshold bit shift
...
Newer BCL hardware doesn't have the threshold registers bit shifted
compared to the ADC measurement register. Add a new flag
qcom,pmic7-threshold, which needs to be added for these new targets so
that the software driver will account for the bit shifting in the
threshold calculation.
Change-Id: I6bc33f14a2717e060c9d32d199df10cc269ca6f1
2020-06-29 11:25:28 -07:00
Tao,Zhang
68bcee4d37
ARM: dts: msm: Add coreisght device tree for shima
...
Add coresight config to device tree for shima.
Change-Id: I39fee1e3f550d09ee81bacf189a6e571a6d5c071
2020-06-29 20:20:58 +08:00
