qctecmdr
b4e5b3bf29
Merge "ARM: dts: msm: Enable smmu for SD card on Lahaina"
2020-04-15 20:35:57 -07:00
qctecmdr
89473ab7ec
Merge "ARM: dts: msm: Add clock required for IPA QoS configuration"
2020-04-15 15:21:55 -07:00
qctecmdr
d9d9403731
Merge "ARM: dts: msm: Add ARM PMU node for Shima"
2020-04-15 15:21:55 -07:00
qctecmdr
d1069f73af
Merge "bindings: clock: Add support for SHIMA clock controllers"
2020-04-15 04:56:57 -07:00
qctecmdr
20416ff138
Merge "ARM: dts: msm: Update ddr bandwidth levels for A660"
2020-04-15 04:56:57 -07:00
qctecmdr
65143bb24b
Merge "ARM: dts: msm: Add charger reference to USB node on Lahaina"
2020-04-15 04:56:54 -07:00
qctecmdr
162b6d0cf6
Merge "bindings: input: qcom-hv-haptics: add nvmem to store CL brake settings"
2020-04-14 17:13:40 -07:00
qctecmdr
2255207857
Merge "Revert "ARM: dts: msm: increase ipa modem smem size to 36k on Lahaina""
2020-04-14 17:13:40 -07:00
Chaitanya Pratapa
a6b356bade
Revert "ARM: dts: msm: increase ipa modem smem size to 36k on Lahaina"
...
This reverts commit bdefb3d72c
2020-04-14 11:18:06 -07:00
Mohammed Mirza Mandayappurath Manzoor
a6bb5bb0a1
ARM: dts: msm: Update ddr bandwidth levels for A660
...
Update available ddr frequencies for each power level to optimize
performance per watt.
Change-Id: I5bd4b49b49ddc369902c03c2dd141f8cf8f5fb70
2020-04-14 09:34:30 -07:00
Mukesh Ojha
5093e8c75f
ARM: dts: msm: Add ARM PMU node for Shima
...
Add the ARM CPU Performace Monitor Unit (PMU) device-tree node
for measuring various CPU performance events such as cycles,
cache misses, and so on.
Change-Id: Ia83421af6a1c168aa497707931e0595743fc7030
2020-04-14 07:10:43 -07:00
Fenglin Wu
348b074d3a
bindings: input: qcom-hv-haptics: add nvmem to store CL brake settings
...
Add properties to specify nvmem for haptics which can be used for storing
closed-loop brake calibration settings.
Change-Id: I59c84a3a0e93229d809f4933bbbcce19249687e9
2020-04-14 10:29:51 +08:00
Fenglin Wu
719ee15464
bindings: input: qcom-hv-haptics: Add qcom,fifo-empty-threshold
...
Add optional property "qcom,fifo-empty-threshold" to specify the
FIFO empty threshold. The module would generate fifo-empty
interrupt when the number of samples in the FIFO is less than this
threshold.
Change-Id: Iceeb2d806bf6115f9fc557b656b06bb22cb77dd4
2020-04-14 10:28:51 +08:00
Mike Tipton
c4b397d41d
ARM: dts: msm: Add clock required for IPA QoS configuration
...
Add additional clock required for IPA QoS register access and
configuration.
Change-Id: I6323f93563a7efeb9115acddc218d4db35636215
2020-04-13 19:14:19 -07:00
qctecmdr
8fa23e4ed7
Merge "ARM: dts: msm: Add LLCC entry for Shima"
2020-04-13 15:42:51 -07:00
qctecmdr
0d395cf1ef
Merge "ARM: dts: msm: increase ipa modem smem size to 36k on Lahaina"
2020-04-13 15:42:51 -07:00
Chandra Sai Chidipudi
5866be0732
ARM: dts: msm: Add LLCC entry for Shima
...
Add Last Level Cache Controller (LLCC) device tree
node for Shima.
Change-Id: I0812f5590ed48c2b1a9617aa4ae7fa6a204452ef
2020-04-13 15:30:51 +05:30
Chandra Sai Chidipudi
2fdbcdbeec
ARM: dts: msm: Add ipcc test nodes for Shima
...
Add IPCC test nodes for adsp, cdsp for Shima. This allows
testing IPCC ping from APPS to these subsystems.
Change-Id: I49f6218f3a932df3ab422418f221a2591ceb7a18
2020-04-13 15:26:31 +05:30
qctecmdr
ba4084fde3
Merge "dt-bindings: i2c-msm-geni: Add DT bindings for le-vm flag"
2020-04-12 19:05:43 -07:00
qctecmdr
5a750d2a1c
Merge "ARM: dts: msm: add stub interconnect devices for SHIMA"
2020-04-12 08:11:30 -07:00
qctecmdr
33e20e9e12
Merge "ARM: dts: msm: use voltage mitigation for pop mem in lahaina"
2020-04-12 08:11:30 -07:00
qctecmdr
b6496924b5
Merge "dt-bindings: Add documentation for the "non-coherent" SMMU dt-binding"
2020-04-11 21:33:07 -07:00
qctecmdr
81091ff5a5
Merge "ARM: dts: msm: Update the RPMHCC node for SHIMA"
2020-04-11 21:33:07 -07:00
qctecmdr
5717772506
Merge "dt-bindings: thermal: Use the correct vendor string for voltage device"
2020-04-11 21:14:43 -07:00
qctecmdr
d3e5bb6fff
Merge "ARM: dts: msm: Update QMP Phy init sequence for Lahaina"
2020-04-11 13:28:32 -07:00
qctecmdr
6ae8a5b12b
Merge "ARM: dts: msm: Add dcc registers lists for lahaina"
2020-04-11 13:28:32 -07:00
qctecmdr
1eba8717c0
Merge "ARM: dts: msm: Add clocks for UFS QOS configuration on Lahaina"
2020-04-11 13:28:32 -07:00
qctecmdr
b0cec9c722
Merge "ARM: dts: msm: Remove epss_l3_shared node"
2020-04-11 13:28:31 -07:00
qctecmdr
3ecf6cf9fb
Merge "ARM: dts: msm: Add LPM support for sm8150"
2020-04-11 13:28:31 -07:00
qctecmdr
5a03fa02a7
Merge "ARM: dts: msm: Add spss glink ssr entry for Lahaina"
2020-04-11 13:28:31 -07:00
qctecmdr
d2263a3c4d
Merge "ARM: dts: msm: do not compile Non-VM specific DT files"
2020-04-11 13:28:31 -07:00
Murali Nalajala
4eba18c97f
ARM: dts: msm: do not compile Non-VM specific DT files
...
Do not compile platform specific DT files if the VM configs are defined.
Compiling platform specific DT files for VMs which are required lead to
compilation errors.
Change-Id: Id47ab2f2cf77a5a04deadbcc0a3e4d31b5e51989
2020-04-09 14:23:17 -07:00
Elson Roy Serrao
ba6ab37ffa
ARM: dts: msm: Update QMP Phy init sequence for Lahaina
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Update the QMP phy init sequence as per the HSR v1.08 and HSR v0.94
update for DP Combo phy and Uni Phy respectively.
Change-Id: I0fd5bd28abe2db64106bf17ff6480ef13f77612e
2020-04-09 11:55:01 -07:00
Mao Jinlong
6dd6e1ce07
ARM: dts: msm: Add dcc registers lists for lahaina
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Add dcc registers lists to support dcc register dump.
Change-Id: I9c5e277cc677a5c1a91540f11fe585d985f58e11
2020-04-09 06:36:57 -07:00
qctecmdr
230630d6ba
Merge "dt-bindings: interconnect: add interconnect bindings"
2020-04-09 04:56:29 -07:00
qctecmdr
5ca27100cc
Merge "ARM: dts: msm: Add cdsp rpmsg entry in Lahaina"
2020-04-09 04:56:29 -07:00
qctecmdr
d94a708261
Merge "ARM: dts: msm: Remove NFC I3C DT node for Lahaina"
2020-04-09 04:56:29 -07:00
qctecmdr
4bbb66b47a
Merge "ARM: dts: msm: Add IMEM entry for Shima"
2020-04-09 04:56:29 -07:00
Taniya Das
52a08e9199
ARM: dts: msm: Update the RPMHCC node for SHIMA
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Update the RPMHCC node to use the RPMH clock driver and move the dummy
rpmhcc to RUMI.
Change-Id: If26c8457ad61c2e7b205885d80650b9933ee73f5
2020-04-09 16:15:05 +05:30
Gaurav Singhal
fe74818d16
ARM: dts: msm: Remove NFC I3C DT node for Lahaina
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Remove device node of NFC I3C for MTP, CDP and QRD platforms.
Change-Id: I73f2661bf436b42054893e94dd004a2667fb1148
2020-04-09 01:57:04 -07:00
Mike Tipton
88b8a8602c
ARM: dts: msm: Add clocks for UFS QOS configuration on Lahaina
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Add clocks required for UFS QOS register access and configuration.
Change-Id: I5eb6ba4a3ebe6e592ed9fa2ac34e8648e73d1926
2020-04-09 00:07:42 -07:00
qctecmdr
f99558c8ed
Merge "ARM: dts: msm: add proxy consumers for L2B and L1C regulators on Lahaina"
2020-04-08 23:18:57 -07:00
qctecmdr
62f97fe736
Merge "ARM: dts: msm: Add "regulator-allow-set-load" for PM8350B IBB regulator"
2020-04-08 19:18:56 -07:00
qctecmdr
fef3cd6637
Merge "ARM: dts: msm: Set no-status-check-on-disable for Lahaina PCIe GDSCs"
2020-04-08 19:18:56 -07:00
qctecmdr
6e8bf32d39
Merge "ARM: dts: msm: Add USB nodes for Shima"
2020-04-08 19:18:56 -07:00
Ram Chandrasekar
efb4dcff49
ARM: dts: msm: use voltage mitigation for pop mem in lahaina
...
Pop mem rule right now mitigates gold and gold+ CPUs separately based on
frequency. Use the voltage mitigation device instead to bring the APC1
voltage for lahaina.
Change-Id: I62103a825a8b6675104777ad0735f9d3515192c1
2020-04-08 16:24:17 -07:00
Ram Chandrasekar
84a4f0a0e2
ARM: dts: msm: Enable CPU voltage cooling device for lahaina
...
Enable CPU voltage cooling device for APC1 cluster including cpu 4 and 7
for lahaina. This will enable thermal framework to achieve voltage
reduction in APC1 rail by bringing down both gold and gold+ frequency
based on voltage.
Change-Id: I61b8767bb4c3999358d05e37903caaf144f46005
2020-04-08 16:24:12 -07:00
Ram Chandrasekar
a60fa1e7a0
dt-bindings: thermal: Use the correct vendor string for voltage device
...
Use the correct vendor string qcom instead of qti to adhere with the
vendor prefix documentation.
Change-Id: I72761a9a188a1b4ad550e2493cb2b1c213dbac3f
2020-04-08 16:19:49 -07:00
qctecmdr
b851d4e70d
Merge "ARM: dts: msm: Add pinctrl for PM8350C GPIO 9 on Lahaina platforms"
2020-04-08 03:42:48 -07:00
Odelu Kukatla
613e71ed70
ARM: dts: msm: add stub interconnect devices for SHIMA
...
Add stub interconnect devices for aggre1_noc, aggre2_noc,
config_noc, dc_noc, gem_noc, lpass_ag_noc, mc_virt_noc,
mmss_noc, nsp_noc, system_noc, This will allow consumers
to get their path and set bandwidth constraints on them.
Change-Id: I2de50b8071c2b3b38da596b360cd9ac87156db82
2020-04-08 10:58:07 +05:30
