Enable voltage cooling device for lahaina. This will enable to build
voltage cooling device using CPUs sharing the same rails.
Change-Id: Ic4df305280006c60bfe3f0287138477a679237c1
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
A single CPU cluster can have CPUs with different frequency plans.
Mitigating individual CPU may or may not bring down the CPU cluster
voltage depending on the operating level of the other CPUs.
CPU voltage cooling device will provide support to apply CPU frequency
mitigation on different CPUs in a cluster to achieve a reduction in
cluster voltage. This is achieved by building a mitigation table mapping
the frequency of different CPUs based on voltage.
Change-Id: Ie09375c6c15a9f81e663fca96c5af87e0b6789c2
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Currently, the cap-id for Tx and Rx of the message-queue are
initialized with 0. However, 0 is a valid value for cap-id.
A better value to initialize the cap-id is with U64_MAX. Hence,
make corrections to use U64_MAX, defined as HH_CAPID_INVAL, in
the message-queue driver.
Change-Id: Ia501e87dc3cb8d880ea3d35ff000ca07b64aeced
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
Add spin_lock_init for funnel and replicator to avoid spinlock issue.
Change-Id: I6cb14bfd363e8d92070af2e0e99e60eaf45d923b
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
Current driver will check PCIe link status by reading PCIe config space
before updating time sync registers. However, there is a drawback to use
PCIe API pci_read_config_word() to access config space since it will
disable interrupt and then perform read. If PCIe link is in L1 or L1ss
state, there may be more than 4ms needed to change the link state to L0
in order to access so it will cause jank for other time critical tasks.
Hence make sure PCIe link is in L0 state before updating time sync
registers instead of checking config space.
Change-Id: I59ca63c38b5af9e38e5a04d8e679f4dfde294746
Signed-off-by: Yue Ma <yuem@codeaurora.org>
Media and USB Video Class drivers are needed to get USB video
devices functional in USB host mode. Hence enable media and USB
video class drivers on Lahaina.
Change-Id: I70ccc146b55a564b4408496a54b044d52cbf9e41
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Adding inrout buffer CMO support with new cache flush logic
involving offsets and overlaps.
Acked-by: Deepika Singh <dsi@qti.qualcomm.com>
Change-Id: I1e5ac1e3c52c80d40b6c3a0c9207e7a73d06bf65
Signed-off-by: Mohammed Nayeem Ur Rahman <mohara@codeaurora.org>
Enable memory dump driver to be build as a module in the defconfig
on Lahaina.
Change-Id: I284e5d082d5a595f794b15fd66163137596e714e
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
Add support to build the memory dump driver as moudle on gki build.
Change-Id: I8cf227d0b0044b935bbf224d1191ec84fa497509
Signed-off-by: Mao Jinlong <jinlmao@codeaurora.org>
Driver reports sensor data without modifying the
orientation of axes.
Change-Id: I3e0d3d3efc848d7e72a1edda9f168721dbccb308
Signed-off-by: rbandi <rohitbandi@codeaurora.org>
Enable LKDTM module for various test cases in the qgki-debug
configuration of Lahaina.
Change-Id: Id0479ec95d8410e52bc270f907e8a537e73d0fb3
Signed-off-by: Prakruthi Deepak Heragu <pheragu@codeaurora.org>
GPIOs that can be configured as wakeup sources, have their
interrupt lines routed to PDC interrupt controller. Add the
interrupt map of the GPIO's to its wakeup capable interrupt
parent.
Change-Id: I6680a6d55f53936ace4daab1f2365de055a89a06
Signed-off-by: Srinivas Rao L <lsrao@codeaurora.org>
Add PDC interrupt controller chip support for shima.
Change-Id: I8d92ccba39ac09eede3236780f0509f6a4b117f1
Signed-off-by: Srinivas Rao L <lsrao@codeaurora.org>
