A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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Author SHA1 Message Date
qctecmdr
1a1bc40c8d Merge "ARM: dts: msm: correction to adsp variant read entry" 2020-09-02 08:39:48 -07:00
qctecmdr
5ad4f3bf08 Merge "ARM: dts: msm: add cont splash memory for shima target" 2020-09-02 08:39:48 -07:00
qctecmdr
0ea93719c2 Merge "ARM: dts: msm: Enable qcom,vmid-cp-camera-preview-ro on Lahaina" 2020-09-02 08:39:47 -07:00
qctecmdr
672ab3d41c Merge "ARM: dts: msm: Add dpdm supply for PM7250b for holi" 2020-09-02 08:39:47 -07:00
Krishna Manikandan
3be4a38579 ARM: dts: msm: add cont splash memory for shima target 
Add cont splash memory node containing base address
and size for shima target.

Change-Id: Ied6a72ec7a6a48f4ccb32f2c268266288292d97b
 2020-09-02 17:20:22 +05:30
Vangala, Amarnath
4e63ed8ec1 ARM: dts: msm: correction to adsp variant read entry 
Correction to the number of bits read for adsp variant identification.
Include adsp_variant read entry for holi-atp variant.
Update dtsi for ATP variant.

Change-Id: I6b95d9f7b1e9a7196195b2e9cc29eae0567ba716
 2020-09-02 16:12:59 +05:30
qctecmdr
59292bd0f1 Merge "ARM: dts: msm: Modify reset cti to cti6 for shima" 2020-09-02 03:12:21 -07:00
qctecmdr
41c043712a Merge "ARM: dts: msm: Add jtagv8 devices for shima" 2020-09-02 03:12:21 -07:00
qctecmdr
30192b2f38 Merge "ARM: dts: msm: alter size for QUPv3 SE4 for lend" 2020-09-02 00:22:29 -07:00
qctecmdr
b9e79ea895 Merge "ARM: dts: msm: update cpu7 L3 latfloor on lahaina" 2020-09-02 00:22:29 -07:00
qctecmdr
8117256ca9 Merge "ARM: dts: msm: Add cpu7 qos latfloor device on lahaina" 2020-09-02 00:22:29 -07:00
qctecmdr
3fa5c4ad5c Merge "ARM: dts: msm: increase L12C regulator max voltage for Lahaina" 2020-09-02 00:22:29 -07:00
qctecmdr
24b1762de5 Merge "ARM: dts: msm: Add domain names for the core lpm nodes for holi" 2020-09-02 00:22:29 -07:00
qctecmdr
9fd9b2e6e0 Merge "ARM: dts: msm: change OVERRIDE_X1 according hardware change of lahaina QRD" 2020-09-01 21:42:14 -07:00
qctecmdr
b090149687 Merge "ARM: dts: msm: Add support for ION for the shima-VM" 2020-09-01 21:42:14 -07:00
Linyu Yuan
d1343f7b35 ARM: dts: msm: change OVERRIDE_X1 according hardware change of lahaina QRD 
USB2 hardware changed and update parameter according.

Change-Id: Iddc1920b5c2bbe87949d5c8d6284f39829180ebc
 2020-09-02 10:17:25 +08:00
qctecmdr
70c014e079 Merge "ARM: dts: msm: Add ice core clock node for holi" 2020-09-01 17:18:52 -07:00
qctecmdr
d2e8211abb Merge "ARM: dts: msm: Disable lpm" 2020-09-01 17:18:52 -07:00
qctecmdr
68792a4de3 Merge "ARM: dts: msm: Add ice core clock node for shima" 2020-09-01 17:18:52 -07:00
qctecmdr
28c4e26499 Merge "ARM: dts: msm: Add support for performance lock on HOLI" 2020-09-01 17:18:52 -07:00
Amir Vajid
6deff4eb8d ARM: dts: msm: Add cpu7 qos latfloor device on lahaina 
Create a qos latfloor device on Lahaina to cover compute
bound workloads running on cpu7 above 2.0 GHz.

Change-Id: Ided709511ff1840ff41ebd8f924f1f5af9350420
 2020-09-01 16:21:41 -07:00
Amir Vajid
182d7a8616 ARM: dts: msm: update cpu7 L3 latfloor on lahaina 
Update the cpu7 L3 latfloor device on lahaina to only
operate on cpu7 with a threshold of 2.0 GHz.

Change-Id: Icf200b5e4d1408a7591d4d3a584e5793c281eb5f
 2020-09-01 16:16:14 -07:00
David Collins
7d45c7687b ARM: dts: msm: increase L12C regulator max voltage for Lahaina 
Increase the maximum allowed voltage for PM8350C LDO 12 (L12C).
This ensures that display panels on Lahaina MTPv2.1 boards
operate correctly where higher IR voltage drop is seen.

Change-Id: Ia864a06ef055de6397c3d40cf5dc489427ff757a
 2020-09-01 14:48:15 -07:00
qctecmdr
b3990d9115 Merge "ARM: dts: msm: PMIIC regulator and platform update for shima" 2020-09-01 14:37:02 -07:00
qctecmdr
1fc39937db Merge "ARM: dts: msm: add cluster power down state for Trusted VM" 2020-09-01 14:37:02 -07:00
qctecmdr
b2882b7036 Merge "ARM: dts: msm: Add GPU_CPR register space" 2020-09-01 14:37:02 -07:00
qctecmdr
2fe155c761 Merge "ARM: dts: msm: Add secure carveout ION heaps for Shima" 2020-09-01 11:50:47 -07:00
Kiran Gunda
da433f3fd2 ARM: dts: msm: PMIIC regulator and platform update for shima 
1. Reduce the min-voltage of L1I, L2I, L5I, L1J, L2J and L3J to
   align with the respective parent min-voltages to avoid the higher
   voltage vote during the LDO disable which leads to higher
   power numbers.
2. Change the min-voltage of SMPS9B as per the HW recommendation.
3. Disable PM8008 and flash led nodes for shima ATP as these are
   not supported for ATP platform.

Change-Id: I0b9aa510ec23a7a16b5cdc50bfd059ad0e4bc002
 2020-09-01 10:39:52 -07:00
Lina Iyer
6d6fbd1449 ARM: dts: msm: add cluster power down state for Trusted VM 
Add cluster idle state for Trusted VM. Since the Trusted VM does cpuidle
using Platform Coordinated PSCI mode, specify the cluster power down as
a idle state in the CPU node.

Change-Id: I245530ac738ab7e35e9bd5c5d81e58a93eb178fa
 2020-09-01 11:31:46 -06:00
Raghavendra Kakarla
cac96efd9a ARM: dts: msm: Add domain names for the core lpm nodes for holi 
Adds the corresponding domains name for the core lpm nodes and
adds the reg-names for top lpm node so that differentiate the
RIMPS addresses for each domain.

Change-Id: Ia086943cc7e86c3518464ce7d00b8e2448922861
 2020-09-01 22:12:37 +05:30
qctecmdr
77e0aebe94 Merge "ARM: dts: msm: Correct PWM-LPG base addresses for PM6150l" 2020-09-01 09:04:13 -07:00
qctecmdr
66f81bcdf4 Merge "ARM: dts: qcom: Update pm7250b alram sensor thermal config for HOLI" 2020-09-01 09:04:13 -07:00
qctecmdr
73825d4c8d Merge "ARM: dts: msm: add property to detect wcd937x in soundwire master" 2020-09-01 09:04:13 -07:00
qctecmdr
3d753d5e18 Merge "ARM: dts: msm: Added psci node for sdxlemur" 2020-09-01 09:04:13 -07:00
Tushar Nimkar
03d42963f9 ARM: dts: msm: Added psci node for sdxlemur 
This changes adds psci node to devicetree and enable psci
driver to initialize.

Change-Id: I1f31d5ced3d0867c2862ea09187da780e512459a
 2020-09-01 05:35:29 -07:00
Jishnu Prakash
968974fb97 ARM: dts: msm: Add dpdm supply for PM7250b for holi 
Add dpdm supply for PM7250b for holi.

Change-Id: Id860c355a7d92a6ac607e041eaece5e2e0dde1c9
 2020-09-01 16:50:39 +05:30
qctecmdr
a589fdf7fc Merge "ARM: dts: msm: Enable TCSR enable check for EUD" 2020-09-01 03:34:50 -07:00
qctecmdr
ca0ee10383 Merge "ARM: dts: msm: Add the interrupts for the APPS TGU for holi" 2020-09-01 03:34:50 -07:00
qctecmdr
26602fe09a Merge "ARM: dts: msm: Enable L3 interconnect driver for Shima" 2020-09-01 03:34:49 -07:00
qctecmdr
98b46477d5 Merge "ARM: dts: msm: Add support of cma heap" 2020-09-01 03:34:49 -07:00
qctecmdr
2c4ef1b38c Merge "ARM: dts: msm: enable USB1 host mode on lahaina HDK" 2020-09-01 03:34:49 -07:00
Gopala Krishna Nuthaki
c7a22b2cfa ARM: dts: qcom: Update pm7250b alram sensor thermal config for HOLI 
Add pm7250b pmic alram thermal zone mitigation with battery
cooling device.

Change-Id: Icd51766dcbbc78ddaa7fd18e3965454c6dd96473
 2020-09-01 02:16:51 -07:00
Taniya Das
820ee3381c ARM: dts: msm: Add support for performance lock on HOLI 
The cpufreq-hw requires the performance lock registers to be updated in
the cases where the SW DCVS is requested.

Change-Id: I6ac45a577904171a051c84b983363d9a2ea1164d
 2020-09-01 09:29:56 +05:30
Taniya Das
7a315b1690 bindings: cpufreq-hw: Add binding support for performance lock 
Add the new optional binding to support perf-lock for CPU.

Change-Id: Ibbd9aac72666bfe635c9965066cb332d4ecd1ab1
 2020-09-01 09:29:41 +05:30
Tao,Zhang
ec67f3b018 ARM: dts: msm: Add jtagv8 devices for shima 
Jtagv8 driver can be used to save and restore debug and ETM
registers across power collapse.

Change-Id: If322843d066e77f5b3aa2b78f2c7b913f6418d8b
 2020-09-01 10:54:53 +08:00
Faiz Nabi Kuchay
ce7280c09f ARM: dts: msm: Add support of cma heap 
Add support of cma heap for shima.

Change-Id: Iaff7c9fb651d1a99511696f6ce3d9f11e6516c7a
 2020-09-01 00:41:58 +05:30
Jishnu Prakash
00d276a268 ARM: dts: msm: Correct PWM-LPG base addresses for PM6150l 
Remove sizes specified in base addresses of PWM-LPG devices
to follow the convention of msm-5.4 to use base addresses
alone without specifying size.

Change-Id: I7d925f5286701696deb5c472897d6f2bf23f475f
 2020-08-31 22:14:24 +05:30
Odelu Kukatla
7a5fc06936 ARM: dts: msm: Enable L3 interconnect driver for Shima 
Enable L3 interconnect driver so that consumers are
able to obtain their path handles properly.

Change-Id: I088da57a382840050c2c539c97b1b5dc2f5d86b3
 2020-08-31 07:11:32 -07:00
Faiyaz Mohammed
f1545f6467 ARM: dts: msm: Add support for ION for the shima-VM 
Add support for ION, and the trusted UI dynamic carveout
heap, for the shima-VM.

Change-Id: I463d425ab368946f35a5951b76bedd61ab4f3191
 2020-08-31 06:41:37 -07:00
qctecmdr
03417227c2 Merge "ARM: dts: msm: Enable QoS programming for HOLI" 2020-08-31 03:20:21 -07:00