In case of composition switch there is a possibility of run/stop
bit gets cleared in the middle of a control transfer. If controller
has cached a SETUP packet but not yet written it to ep0 TRB, controller
halt fails even if there are no pending events in event ring. As part of
pull up enable run/stop bit gets set and control transfer starts, due to
that controller writes cached SETUP packet to ep0 TRB and triggers xfer
completion. Since run/stop bit is set Host issues bus reset and end
transfer and Halt are issued on ep0 because ep0 is not in SETUP phase.
However this does not recover the controller's ep0 state machine. As a
result controller is unable to handle SET ADDRESS SETUP packet issued by
host.
Before completing data stage of control transfer if vbus disconnects
controller halt fails even after issuing end transfer cmd on ep0 IN.
There is a possibility of race between controller accessing the ep0
buffer from cached TRB which was queued in data stage of control
transfer and end xfer command completion. This is resulting into
accessing of TRB buffer after controller halt failure by this time
buffer is already unmapped by dwc3_remove_requests().
Fix above issues by issuing core soft reset if control halt fails to
prevent controller from accessing cached TRB buffer. Also move issuing
of end xfer command for ep0 IN before un-mapping the ep0 TRB buffer in
case ep0 state is not in SETUP phase in dwc3_remove_requests().
Change-Id: Ie159e06a2537afcc9deee3f6670aac5d66b97b90
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
Signed-off-by: Elson Roy Serrao <eserrao@codeaurora.org>
While doing usb disconnect the ep0 is disabled, therefore
when composite_setup tries to queue on ep0 endpoint,
the operation result in race between the two functions
leading slab poison error since the request is already freed.
Fix this by disabling irqs, introducing flush for any
pending works to be cleared and enabling the irqs back.
Change-Id: I82f7a428929905762bae17dedbe717e0110155c5
Signed-off-by: Udipto Goswami <ugoswami@codeaurora.org>
After clearing run/stop bit there might be events still pending
with the controller which will not allow the controller to be
halted. Fix this by simply clearing GEVNTCOUNT(n) by reading and
writing back the counts.
Change-Id: Id93df8effe73b1765cced65590679b7df6c232da
Signed-off-by: Pratham Pratap <prathampratap@codeaurora.org>
Remove unused register offset related enums as those are not used
for configuration within USB PHY driver. This helps to reduce
number of register offset value need to pass from devicetree with
USB QMP PHY device node.
Change-Id: Ia0581c3dc8210bfaac9a7318eb75e1ffa35440b6
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
dma_zalloc_coherent() is no longer needed and get deprecated as it has
no users because dma_alloc_coherent() already zeroes out memory for us.
Change-Id: Ibd49d7afce8caaa7b2b6aed61884b307674f9a59
Signed-off-by: Bojun Pan <bojunp@codeaurora.org>
SENSORS_SSC module is dependent on the SSR subsystem
so, update Kconfig dependency details.
Change-Id: Iaba55723485d038c11931ac8914665af35a26a3e
Signed-off-by: Jun-Hyung Kwon <junhyung@codeaurora.org>
Update APIs used in fastrpc driver according to the new function
signatures on the Lahaina branch.
Change-Id: I979e116ab7e7019e4f17e84f1672f6c8bb30e2e8
Signed-off-by: Edgar Flores <edgarf@codeaurora.org>
When checking if a domain is a atomic or not, the driver code
will take the bitwise AND of the 64-bit domain attributes field
and a bitmask with bit 32 set. This value is then implicitly cast
to an int, which truncates the upper 32 bits--losing the bit
that indicates if the domain is atomic or not--and based on
that int, we determine if the domain is atomic, which will
vacuously be false.
Instead, check if the bitwise AND operation yields a non-zero
value when determining if a domain is atomic or not to prevent
any truncation errors.
Change-Id: I96753035b47b848bc4d1e8029c8f3f46e03f8c67
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Signed-off-by: George Shen <sqiao@codeaurora.org>
In the LAN rx data path the status packet was parsed twice
but in the second time it parsed not all the info was needed.
So we added a function that is tailored for that scenario
to improve performance.
Acked-by: Tal Gelbard <tgelbard@qti.qualcomm.com>
Change-Id: I8a1755ba62cee4147941b5949c2b223fe76415b2
Signed-off-by: Amir Levy <alevy@codeaurora.org>
Added a flag in the 11ad driver to indicate if NAPI is
enabled in the LAN RX Datapath. In case the flag is true
the 11ad driver will now use napi_gro_receive instead of
netif_rx_ni, meaning the GRO feature is also enabled
with this change.
Acked-by: Tal Gelbard <tgelbard@qti.qualcomm.com>
Change-Id: I5c6cb3e08c29c4b79cdcbc9e4d3acb485156a607
Signed-off-by: Amir Levy <alevy@codeaurora.org>
Add debug log to show which CPU dai is not registered
during bootup.
Change-Id: Ia6324edec64ff6e7ee08a0b292259c8ffb70d20e
Signed-off-by: Meng Wang <mengw@codeaurora.org>
Because of not updated mask and shift value, IPA HW not able to
process the forcce close command and asserting with invalid command
offset. Add changes to update mask and shift values for aggregation
force close register.
Change-Id: I19164a32c6a5d49fb005c4a09eb95a23a5d4b6ec
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
During IPA shutdown the allocation for memory request fails.
Add changes in IPA to not sleep while memory allocation.
Change-Id: I0adb09e32970ff1d67c3249bb9d3c9dbdc970a8a
Signed-off-by: Praveen Kurapati <pkurapat@codeaurora.org>
Add a missing dma_unmap_single() that was accidentally deleted when adding
tracepoints in the secure_buffer driver.
Change-Id: I8159bee354b4debffb2a55165d2e543d5979daff
Signed-off-by: Chris Goldsworthy <cgoldswo@codeaurora.org>
