Enable CONFIG_SHADOW_CALL_STACK_VMAP by default, and as we allocate
a full page for the stack, allow the kernel use all of it.
Bug: 169781940
Change-Id: Ie8eaa7f24e9bf10ff28a302ac98ad843b71c9c2a
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Git-commit: 1eb128820e
Git-repo: https://android.googlesource.com/kernel/common/+/refs/heads/android11-5.4
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>
The proxy consumer driver currently only supports proxy
probing for platform bus. However, there's a need to
proxy-probe coresight devices, which falls under ABMA bus.
Hence, extend the driver to support proxy probing for
"struct amba_driver" and add coresight-etm ids to the list.
Change-Id: I48da20ea18f61b5cc82ae0616a75c23af32481a2
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
Add "qcom,jtagv8-mm" to the list of proxy consumers, such that
the sync-state logic need not wait for the probe from the actual
driver if it's disabled.
Change-Id: I580a865ba3c4c298d76e29552eec854b33faea24
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
Update the DLL power up sequence according to the latest enhanced SDCC
DLL HSR document and SDCDC initialization sequence in HPG.
Final sequence:
Step 1 - Set PWRSAVE bit in MCI_CLK to '0' during reset
Step 2 - Disable CK_OUT
Setp 3 - Set CORE_DLL_CLOCK_DISABLE to '1'
Step 4 - Set RST & PDN to '1'
Step 5 - Set DLL_CONFIG_3
Step 6 - Set SDC4_USER_CTRL
Step 7 - Set SDC4_TEST_CTRL(SW can Skip this step)
Step 8 - Set DDR_CONFIG
Step 9 - Set DLL_CONFIG_2
Step 10 - Set DLL_CONFIG
Step 11 - Wait for 52 us
Step 12 - Set RST & PDN to '0'
Step 13 - Set RST to '1'
Step 14 - Set RST to '0'
Step 15 - Set CORE_DLL_CLOCK_DISABLE to '0'
Step 16 - Wait for 8000 input clock cycles
Step 17 - Enable CK_OUT
Step 18 - Check for Lock
Step 19 - If PWRSAVE is needed, set PWRSAVE to '1'.
Change-Id: I889937a1728b3ce039a802972f9668969fe96505
Signed-off-by: Jun Li <liju@codeaurora.org>
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
The ufs_reset pin is expected to be wired to the reset pin of the
primary UFS memory but is pretty much just a general purpose output pin.
Reorder the pins and expose it as gpio 204, so that the UFS driver can
toggle it.
Change-Id: Ifd0b430a4c057a4fa5c4a57fb484c71df18d7f1d
Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
Add initial pinctrl driver to support pin configuration with
pinctrl framework for sdmshrike. This driver is a snapshot of
pinctrl-sdmshrike.c from msm-4.14 at commit id "54fbb7a2".
Change-Id: I8585c025cee91e5cce75598ed2e43cdc00bb769a
Signed-off-by: Saurabh Ambulkar <sambulka@codeaurora.org>
Populate egpio related variables in pingroup macro. This is
to make sure pincontrol-msm driver takes epgio bits into
account when it configures pinmux setting for any tlmm pin.
Change-Id: I828661fd2e05664b583dc40d3110096a95a489e8
Signed-off-by: Vivek Kumar <vivekuma@codeaurora.org>
Add option to enable the compilation for SA8195
platform.
Change-Id: I0866efa419c213d842448b35ee4a829785e7d954
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
Add option "ARCH_SA8155" to enable compilation
for sa8155 target.
Change-Id: I55af2e604c946f8d0494ed6b9ad53aa42244b596
Signed-off-by: Shreyas K K <shrekk@codeaurora.org>
During char device creation, device counted by chdev_count and since
the device creation can happen from different contexts, need to guard the
flow.
This change introduces new lock for spcom_dev->chdev_count.
Change-Id: If59c3ae69d7366892583b2552cf276b6714eeb03
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
The votes for power resources can only be removed if there are no
outstanding TLB invalidation operations. This is true when the
downstream io-pgtable-arm optimizations are in use, as the code that
unmaps the memory from the IOMMU page tables ensures that all TLB
operations are complete before returning.
However, the upstream io-pgtable-arm implementation allows for a TLB
invalidation to be in progress when control is returned back to
arm_smmu_unmap(), at which point the votes for the power resources
will be removed. In cases where the GPU is in slumber, the GPU block
and GPU SMMU get powered down when the SMMU driver removes its votes.
This causes problems where unmapping buffers takes a long time.
For scenarios where it is not feasible to guarantee that TLB
invalidations have completed when control is returned to the
arm_smmu_unmap() function, leave the votes for power resources in place,
and rely on the subsequent sync operation to remove the votes.
Change-Id: Idc594cc69860b44a8eb56c72b5c592bf4799bf84
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Enable CONFIG_UFS_DBG for Holi debug builds, so that UFS Ftrace
logs gets enabled in trace instances.
Change-Id: Id4171a386900931ae1c59853235a3fc2cbe3bc05
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
In an ONFI compliant devices, the flash parameters are calculated
by reading the onfi parameter page of the device.
Existing flash density is calculated based on a single logical
unit(LUN). This shows wrong density information on Multi LUN flashes.
So, always use number of LUNS value in flash density calculations.
Change-Id: Idba4d4e129e7fdcdab1e509bd8c3149f26fc11f2
Signed-off-by: Pradeep P V K <ppvk@codeaurora.org>
Commit 3a1bd738ef ("dma-mapping-fast: Do not clobber existing atomic
pool") included the genalloc.h header file in the dma-mapping.h header
file.
Including genalloc.h in dma-mapping.h expands the definition of the
gen_pool structure for all files that include dma-mapping.h.
This can cause a different CRC value to be generated for an exported
function symbol, if the function parameters or any of their descendant
members contain genpool structures, as the genpool structures may have
been previously forward declared, but now they are fully defined.
Remove the inclusion of genalloc.h in dma-mapping.h to fix this.
Change-Id: I83a3fad284649b91372168d845f30d9302f75c1d
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Enable SD/eMMC card driver as a inbuilt module for sdxlemur target.
Also Enabled the required Block layer configs.
Change-Id: Ide938308ae659cbe558af341dd8697cab3b987d5
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
The haptics module supports writing FIFO samples using 4-byte burst
mode as well as 1-byte mode. During FIFO refilling, if a 1-byte write
was used, then the hardware would fill zeros automatically after that
to keep the FIFO data 4-byte aligned. When this happened in the middle
of playing, the hardware inserted 0 values would cause spurs on the
haptics output. To fix this, only use 4-byte burst writes during FIFO
refilling until the end of the play.
Change-Id: I0441942585e0e0d5da62ec4a7123b2763b292739
Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
QTI implementation for block keyslot manager and
crypto vops for crypto support in CQHCI.
Fixed compilation issues in cqhci-crypto-qti.c and merge
conflicts in sdhci-msm.c and Kconfig files.
(cherry picked from mainline kernel_msm-4.19 commit 5220e65f).
Conflicts:
drivers/mmc/host/Kconfig
drivers/mmc/host/sdhci-msm.c
Test:
1. Device booted upto UI with File Based Encryption enabled.
2. Key insertion using fscryptctl tool.
3. Created new files under /data and checked retention across
multiple re-boots.
4. vts_kernel_encryption_test tests.
5. check_encryption test for verifying metadata encryption.
Change-Id: I9b64f85ca97c269a6ecd6fde2bb693745d4c43d4
Signed-off-by: Neeraj Soni <neersoni@codeaurora.org>
Signed-off-by: Vaibhav Agrawal <vagrawa@codeaurora.org>
Instead of checking PCIe S/W link state, check if the link is on
is on or off to determine whether PCIe resume should be allowed
or not. PCIe S/W link state is not enough to determine since
MSM_PCIE_LINK_DOWN state can be set for link on or off.
Change-Id: I23a27007eb90134c90d5a20034248697423ebeeb
Signed-off-by: Tony Truong <truong@codeaurora.org>
Wire up cqhci.c with the eMMC Crypto API and support for block layer inline
encryption additions and the keyslot manager.
Ported and fixed the merged conflicts in cqhci.c file
Added new member in cqhci_host to get platform device from sdhci
during cqhci_pltfm_init().
(cherry picked from mainline kernel_msm-4.19 commit 2543833e).
Conflicts:
drivers/mmc/host/cqhci.c
Test:
1. Device booted upto UI with File Based Encryption enabled.
2. Key insertion using fscryptctl tool.
3. Created new files under /data and checked retention across
multiple re-boots.
4. vts_kernel_encryption_test tests.
5. check_encryption test for verifying metadata encryption.
Change-Id: I6860cd29d6f044f559385d438048b850faf9a8be
Signed-off-by: Neeraj Soni <neersoni@codeaurora.org>
Signed-off-by: Vaibhav Agrawal <vagrawa@codeaurora.org>
Add functions to use eMMC inline encryption hardware capability
inline with JEDEC eMMC v5.2 specification and to work with
block keyslot manager. Also add crypto variant vops to handle
quirks in individual inline encryption hardware. The vops fallback
to default implementation which is JEDEC eMMC v5.2 compliant.
Fixed the merged conflict in Kconfig file.
Fixed compilation issue in cqhci-crypto.c file.
(cherry picked from mainline kernel_msm-4.19 commit 32f1d1ca).
Conflicts:
drivers/mmc/host/Kconfig
Test:
1. Device booted upto UI with File Based Encryption enabled.
2. Key insertion using fscryptctl tool.
3. Created new files under /data and checked retention across
multiple re-boots.
4. vts_kernel_encryption_test tests.
5. check_encryption test for verifying metadata encryption.
Change-Id: I72b85d572d7c76b966e34b80e7e8eca83a2bb35f
Signed-off-by: Neeraj Soni <neersoni@codeaurora.org>
Signed-off-by: Vaibhav Agrawal <vagrawa@codeaurora.org>
