The "capacity-dmips-mhz" and "dynamic-power-coefficient" are
used to build Energy Model which in turn used by EAS to take
placement decisions.
Change-Id: Ia44ffe4fcb799663c4bb47eb18f1ac79952ed12d
Update PDC node to add missing properties like pdc ranges, spi cfg
register and add it as wakeup parent to TLMM.
Change-Id: I64b1ae4781cf59bb58a930e317ad98aa75c9b19e
Add the DT property "regulator-allow-set-load" for PM8350B IBB
regulator device that is required to support some consumer APIs.
Change-Id: I0a54c4bb7b4e3b6234d36072041ee78fde4774d5
To support new filter/routing tables for dynamic
RSB enablement feature, modem smem size needs to be
increased. Make changes to increase the SMEM size
to 36K.
Change-Id: I5119f26a6c9f366257377384c0eef47e095eb058
Add documentation for CPU voltage cooling device. CPU voltage cooling
device will provide support to apply CPU frequency mitigation on the
different CPUs in a cluster to achieve a reduction in cluster voltage.
This is achieved by building a mitigation table mapping the CPU
frequency levels to a voltage.
Change-Id: I41a222c54442bdc065267f1f1cf079118b8032e9
CDSPRM module relies on the rpmsg node to create a communication
channel with CDSP. The node also carries information for Cx i-peak
limit management, CPU QoS voting, HVX, CDSP thermal mitigation
frameworks.
CDSPRM module implements a RPMSG interface to communicate with CDSP
while providing a way for CDSP to vote for CPU L3 clock, CPU QoS to
benefit CDSP applications performance. The module also implements
an interface with NPU for Cx i-peak limit management and registers
cooling devices for CDSP and HVX thermal mitigation.
Documentation for device tree bindings related to CDSPRM.
Change-Id: I0f79ebcfcd2e6a2366f755278ae2c5f6bc1b8199
Tuning for Tx 3.1 Gen2 needs to be done by modifiying the deemph
registers. Expose these registers via device tree properties so that
tuning can be applied duing dwc3 init.
Change-Id: I84066e976ccbd6006ca9149e29d1c27acb694646
Upgrade Lahaina's memory map to version 5, which entails:
-removing the 30 MB trace buffer that was added for the trusted VM
since it was not needed.
-Moving the trusted apps region and allowing it to grow 23 MB more.
Change-Id: Ib2c259a3b692fc19c144dc41e039dca95bf4fb6c
The register address range for Lahaina is not covering all the
controller registers. Tuning the Tx deemph registers for dwc3
gen2 protocol test is not possible with the current range.
Modify the reg property to cover the entire range as defined in
the data book to fix this issue.
Change-Id: I34b605f920af7cae8b2efd69a54f96e8cde5c001
Output of PWM channel 4 is used for external backlight control of
display panel. Add pinctrl configuration for PM8350C GPIO 9 such that
it is capable of outputting PWM 4's output. This pinctrl configuration
is used by display driver for external backlight control.
Change-Id: Ie9e1a1bf02d8caecde61861dc4528fa0f414a995
Add qcom,msm-hang-detect to device tree to enable MSM Core Hang
Detection on all cores.
Changed from 2 nodes (one for each of silver and gold) to
1 node because that's semantically correct for the driver.
Change-Id: I063d7cc244a0b5d12971f393f45053914fa53179
Secure processor is brought out of reset at the bootloader
stage, so add boot-enabled flag to spcomm.
Change-Id: I0d06c8c657518dfc18b20f4622083f13b697f027
Secure processor subsystem is brough of reset in the
bootloader for the kona SoC, so add boot-enabled flag
support for the SPSS secure pil node.
Change-Id: I1f1d691e1320721a10fcc7e6ec3b2298e643ec99
Use 'dma-coherent-hint-cached' instead of 'dma-coherent' for the
fastrpc iommu context banks.
Now, on a QGKI kernel, cached ION buffers will be DMA mapped as
IOMMU cached for the fastrpc devices, all other buffers will be
DMA mapped as IOMMU uncached and dma_alloc_attrs will always
return memory with a cached CPU mapping as well as DMA mapping
its memory as IOMMU cached.
On a GKI kernel, all buffers for fastrpc devices will be DMA
mapped as IOMMU uncached and dma_alloc_attrs will always return
CPU uncached memory.
Change-Id: I4c5b3e082dc057cb76bfd039b19c6211c729597f
Acked-by: Thyagarajan Venkatanarayanan <venkatan@qti.qualcomm.com>
